You don't say what bandwidth you expect and what you require.
A bit of PLL basics: One fundamental limit to the crossover frequency in a PLL is the loop delay. A practical crossover is around a tenth of the inverse delay. With a few µs ADC sampling and DMA delay, a few µs of filter delay, a few µs processing latency, a few µs DDS update writing and latency that'll get you to about 15 µs delay and 6 kHz crossover.
With a new revision of the design we are hitting that and testing it with the pilot customers that we support. It also has a significantly lower noise floor and reduced spurs. Some rough not-particularly-optimized in-loop phase noise of a loop-back setup near 160 MHz below. Vertical units are dBrad²/Hz, subtract 16 dB to get dBturn²/Hz.
The approach here excels for example on long links, use cases where ultimate low frequency gain and the error feedback matters, and always if the diagnostics, configurability and analysis tools are important. Higher crossovers and high frequency noise on short links need a different approach: a much higher IF or even skipping the analog downconversion stage and correspondingly a different DSP platform and preferably also a different DDS implementation.
Please do submit an issue and/or PR if you have identified a bug.
