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Mirny v1.0 MUXOUT Error / Inconsistent Behaviour
Running independent kernels with DRTIO?
Difference between `archive` and `save`
artiq_master without real hardware
Line Trigger
Installing Xilinx Vivado, Ubuntu variant choice
Vivaod FHC chroot
Problem with running the simple LED.py script
Invalid metadata in ARTIQ Qt platform plugins
Deltaflow-on-ARTIQ - an update
Interfacing with PCI-e hardware
DDS amplitude using set()
Configuring a custom Kalsi Crate
Excessive execution time when creating RF switching events
Displaying custom applets on ARTIQ Dashboard
TTL outputs are not flat
Redundant device manager parameter in the fake Core
Sampling and cotrolling DDS in parallel
GUI for quick control over all devices
output of the TTlout
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