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All Discussions
strange behavior when using gate_rising() function
Phase of multi-tone Phaser output signals
How to fit the data in ARTIQ during experimental run?
Simultaneous control of more than one channel of Zotino
RTIO event submission if lane FIFO is full
Integral const. (K_i) isn't working for the stabilizer to work as a PID
Error while building the Kasli gateware image
Windowing (pulse shaping) Phaser Output
OSError: source code not available
Ignored delays and infinite wait after installing satellite
Parallel control Fastino channels
Issues with running DDS channels from AD9910 and Ad9912
device_db with DRTIO satellite
Does MiSoC Support RT-Linux?
Start immediately after rising edge detected
Best method for retrieving dataset data while inside kernel
Vivado problem during firmware build
RTIO clock frequency for Kasli (cu3)
Proper Alias Format?
ARTIQ Reset
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