occheung Thank you very much for your reply, I tried your suggestion but I am still getting an error. I changed the code to
from artiq.experiment import *
from artiq.coredevice.ad9910 import (RAM_DEST_ASF, RAM_MODE_CONT_RAMPUP)
class DDS_RAM(EnvExperiment):
def build(self):
self.setattr_device("core")
self.servo = self.get_device("suservo0")
self.cpld = self.get_device("urukul0_cpld")
self.dds = self.get_device('urukul0_dds')
# self.setattr_argument("channel", NumberValue(precision=0, step=1))
self.channel = 0
self.ddsCh = self.get_device(f"suservo0_ch{self.channel}")
def prepare(self):
# Reversed Order
self.amp = [1.0, 0.9, 0.8, 0.7, 0.6, 0.5, 0.4, 0.3, 0.2, 0.1, 0.0]
self.asf_ram = [0] * len(self.amp)
@kernel
def init_dds(self, channel, att):
self.core.break_realtime()
self.servo.init()
self.servo.set_config(enable=0)
self.servo.set_pgia_mu(0, 0)
self.cpld.set_att(channel, att)
@kernel
def configure_ram_mode(self, dds, ddsCh):
self.core.break_realtime()
dds.set_cfr1(ram_enable=0)
self.cpld.io_update.pulse(8.)
self.cpld.set_profile(0) # Enable the corresponding RAM profile
# Profile 0 is the default
dds.set_profile_ram(start=0, end=len(self.asf_ram)-1,
step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP)
self.cpld.io_update.pulse(8.)
dds.amplitude_to_ram(self.amp, self.asf_ram)
dds.write_ram(self.asf_ram)
self.core.break_realtime()
ddsCh.set_dds(profile=0, frequency=100*MHz, offset=0.)
ddsCh.set_y(0, 1.)
ddsCh.set(en_out=1, en_iir=0, profile=0)
dds.set(frequency=5*MHz, ram_destination=RAM_DEST_ASF)
self.servo.set_config(enable=1)
# Pass osk_enable=1 to set_cfr1() if it is not an amplitude RAM
dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)
self.cpld.io_update.pulse(8.)
@kernel
def run(self):
self.core.reset()
self.core.break_realtime()
self.cpld.init()
self.init_dds(0, 10.)
self.configure_ram_mode(self.dds, self.ddsCh)
This throws the following error
<synthesized>:1:1-1:70: error: host object does not have an attribute 'pulse_mu'; did you mean 'pulse'?
`<artiq.coredevice.urukul._RegIOUpdate object at 0x000001c2c9550260>`
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
dds_ram.py:50:1: note: expanded from here
def run(self):
^
<artiq>/coredevice/ad9910.py:596:9-596:37: note: attribute accessed here
self.cpld.io_update.pulse_mu(8) # assumes 8 mu > t_SYN_CCLK
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
At this point I am not quite sure which instances of the AD9910 are compatible with the instances of the SUServo, so I would appreciate some clarity in that regard
What we are trying to achieve is to test the card's capability to perform amplitude ramp and how fast the frequency can be changed. So, I was trying to achieve the amplitude ramp as shown in the manual. I am facing some trouble in changing the frequencies quickly as well (not necessarily a ramp, we just want to change it between two values in the order of 100s of microseconds). So, what I am seeking is a better picture of programming the DDS when it is configured to the SU servo mode as there seem to be difference in syntax between the instances of the SU servo class and the AD9910 DDS class.
