Hi,
I was trying to build some gateware for a Kasli 2.0 including a Fastino with log2_width 5. Standalone, that worked fine, but as a DRTIO satellite (or master) the build fails. Reducing the SED lanes to 4 seemed to work (though that is not very practical). I was wondering, is it a known limitation that a Kasli 2.0 build with DRTIO, a Fastino (log2_width 5), and the default number of SED lanes (8) cannot fit into the FPGA?
Using ARTIQ v9.9366+18d1cb9.beta and Vivado 2024.2.
The JSON description:
{
"target": "kasli",
"variant": "kasli_20_fastino_satellite",
"hw_rev": "v2.0",
"sed_lanes": 8,
"enable_wrpll": false,
"drtio_role": "satellite",
"peripherals": [
{
"type": "dio",
"ports": [ 6 ],
"bank_direction_low": "output",
"bank_direction_high": "input",
"edge_counter": true
},
{
"type": "fastino",
"ports": [ 0 ],
"log2_width": 0
},
{
"type": "fastino",
"ports": [ 8 ],
"log2_width": 5
}
]
}
Last part of Vivado output:
Phase 3 Detail Placement | Checksum: 201ad6b65
Time (s): cpu = 00:06:43 ; elapsed = 00:02:51 . Memory (MB): peak = 4010.879 ; gain = 63.473 ; free physical = 31259 ; free virtual = 65303
ERROR: [Place 30-487] The packing of instances into the device could not be obeyed. There are a total of 15850 slices in the device, of which 11571 slices are available, however, the unplaced instances require 1
3442 slices. Please analyze your design to determine if the number of LUTs, FFs, and/or control sets can be reduced.
Number of control sets and instances constrained to the design
Control sets: 1050
Luts: 65957 (combined) 72705 (total), available capacity: 63400
Flip flops: 65031, available capacity: 126800
NOTE: each slice can only accommodate 1 unique control set so FFs cannot be packed to fully fill every slice
ERROR: [Place 30-99] Placer failed with error: 'Detail Placement failed please check previous errors for details.'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Phase 4 Add Constraints
Phase 4.1 Add User PBlocks
Phase 4.1 Add User PBlocks | Checksum: 162f02a1c
Time (s): cpu = 00:06:43 ; elapsed = 00:02:51 . Memory (MB): peak = 4010.879 ; gain = 63.473 ; free physical = 31259 ; free virtual = 65303
Phase 4 Add Constraints | Checksum: 162f02a1c
Time (s): cpu = 00:06:43 ; elapsed = 00:02:51 . Memory (MB): peak = 4010.879 ; gain = 63.473 ; free physical = 31259 ; free virtual = 65303
Ending Placer Task | Checksum: 2037dee81
Time (s): cpu = 00:06:43 ; elapsed = 00:02:51 . Memory (MB): peak = 4010.879 ; gain = 63.473 ; free physical = 31259 ; free virtual = 65303
45 Infos, 1 Warnings, 0 Critical Warnings and 3 Errors encountered.
ERROR: [Common 17-69] Command failed: Placer could not place all instances
place_design failed