Hello,
I met a problem of pll lock fail in one urukul board, that is the front panel red led is on and the frequency output is 160MHz while my setting is 100MHz. Then I would like to check the pll lock status by sta_read() function in urukul cpld class. However, the return shows all 0. How can I get the correct data?
Here is my code.
from artiq.experiment import *
from artiq.coredevice.urukul import urukul_sta_pll_lock, urukul_sta_smp_err
class UrukulPLLCheck(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("suservo0")
self.setattr_device("urukul0_cpld")
@kernel
def read_sta_once(self) -> TInt32:
self.core.reset()
self.core.break_realtime()
delay(200*us)
# Initialize CPLD (reads proto rev, sets up SPI) and give it a moment
self.suservo0.init()
delay(200*us)
self.suservo0.cplds[0].set_att(0, 0.0)
sta = self.suservo0.cplds[0].sta_read()
#sta = self.urukul0_cpld.sta_read()
return sta
def run(self):
sta = self.read_sta_once()
pll_mask = urukul_sta_pll_lock(sta)
smp_mask = urukul_sta_smp_err(sta)
print(sta, pll_mask, smp_mask)