Flash77 atse To anyone that might be seeing this at a later date, I think I managed to fix this issue. The issue was that the fastino module can essentially only respond to the FPGA at a period of 392 ns (I dont exactly understand the issue, you can refer to the github issue)
I was in process of writing wrappers for all the instruments so that I can define a t=0 and schedule pulses at some time say t=50 us wrt this timestamp instead of working with delay statements. So for the fastino module, I ended up aligning all the timestamps to the closest integer multiple of 392 ns and I also aligned the start of the experiment t=0 to the nearest multiple of 392 ns (for this I had to define a timestamp helper class). This in practice means that the pulse lengths I input will be rounded off to a slightly different values and the experiment start will be slightly different, these issues are inconsequential to us, but it seems like the pulses produced from this are free of delays. PFA my codes and the trace
from artiq.experiment import *
import numpy as np
class Timestamp:
def __init__(self, parent):
self.core = parent.core
self.t0 = np.int64(0)
self.dac_period_mu = np.int64(392)
@kernel
def anchor(self):
self.core.break_realtime()
self.t0 = now_mu()
@kernel
def anchor_fastino(self):
self.core.break_realtime()
self.t0 = np.int64(self.dac_period_mu*(now_mu()//self.dac_period_mu))
@kernel
def at(self, t):
at_mu(self.t0 + self.core.seconds_to_mu(t))
from artiq.experiment import *
import numpy as np
class FastinoWrapper:
def __init__(self, parent, timestamp, device_name):
self.core = parent.core
self.dac = parent.get_device(device_name)
self.timestamp = timestamp
self.dac_period = 392*ns
self.dac_period_mu = np.int64(392)
self.dac_latency = 2*us
@rpc(flags={"async"})
def print_ker(self, str):
print(str)
@kernel
def at(self, t):
at_mu(self.core.seconds_to_mu(t) + self.timestamp.t0)
# self.print_ker(self.core.seconds_to_mu(t) + self.timestamp.t0)
@kernel
def at_fastino(self, t):
t_abs_mu = self.core.seconds_to_mu(t) + self.timestamp.t0
t_period_mu = np.int64(self.dac_period_mu*(t_abs_mu//self.dac_period_mu))
at_mu(t_period_mu)
@kernel
def init(self):
self.dac.init()
@kernel
def set_dac(self, t, channel, voltage):
self.at_fastino(t)
delay(-self.dac_latency)
self.dac.set_dac(channel, voltage)
delay(self.dac_latency)
@kernel
def set_dac_pulse(self, t, dt, channel, voltage):
self.set_dac(t, channel, voltage)
self.set_dac(t+dt, channel, 0.)
from artiq.experiment import *
import numpy as np
from timestamp import Timestamp
from ttl_wrapper import TTLWrapper
from fastino_wrapper import FastinoWrapper
class Driver(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("core_analyzer")
self.timestamp = Timestamp(self)
self.ttl = TTLWrapper(self, self.timestamp, "ttl4")
self.dac = FastinoWrapper(self, self.timestamp, "fastino0")
@kernel
def run(self):
self.core.reset()
self.dac.init()
t_period = 392*ns*2
while True:
self.timestamp.anchor_fastino()
self.ttl.pulse(0., 10*us)
self.dac.set_dac_pulse(0., 10*us, 0, 9.95)
self.timestamp.at(20*us)
