How do I (or can I) set up mirny/kasli to have 125MHz SPI clock but 1 GHz RTIO?

mnchow

1.) I'm really looking for a clocking diagram and configuration instructions for Kasli, Mirny, and Urukul.
2.) I want to have 1 GHz RTIO time resolution, but send lower frequency ref clocks to the RF peripherals over MCXX. It looks like in the Kasli block diagram that the MCXX output of the Kasli and the FPGA both use the output of the clock buffer (after multiplication) . Does this mean I need to run both at the same frequency?
3.) Also, how do I configure mirny communication and frequency generation reference clocks?
4.) Finally, is core.ref_period the same as the RTIO fine or coarse timing clock tick?

Thanks in advance. -Matt

architeuthis

core.ref_period is the period after multiplication, i.e. the fine tick or machine unit, i.e. 1 ns in the common 125MHz case.

architeuthis

I want to have 1 GHz RTIO time resolution, but send lower frequency ref clocks to the RF peripherals over MCXX.

To my knowledge this is the usual arrangement. The Mirny PLL IC doesn't take clock input faster than 250/600 MHz.

Also, technically, 1 GHz RTIO time resolution is limited to the high-resolution SERDES PHYs/devices which are actually capable of using the fine timestamp data. It might be helpful to see e.g. this discussion in the repository on fine/coarse timestamps and data, though note that the original issue is from 2019.