airwoodix
I tried your method and the DDS frequency was stuck in the lower limit for >250 us.

I am not sure how to control/eliminate the time gap (where its stuck at lower limit). Couldn't find anything relevant in the datasheet. Alternatively I have fixed the DRCTL pins to high in the CPLD, and just use the increment fields instead. This is what I got by combining the DRG (frequency) and RAM (amplitude).

Amplitude and frequency changes simultaneously at a defined interval.
Are there any interest for this CPLD patch?
Nvm, just enable load LRR @ I/O Update in CFR1. See the DRG usage in ARTIQ.