Sweep frequency DDS

rjo

As always: fund the development and talk to people that can implement it or if you feel up to it, do it yourself.

isaac

rjo Okay, got it.

han94ros

isaac why can't you simulate the ramp using the RAM mode?

isaac

han94ros Thanks for the advice. In fact, I've implemented a workable solution with DMA. But I still think that being able to get direct access to DRG would enable us to tackle the problem in a more elegant way.

occheung

airwoodix
I tried your method and the DDS frequency was stuck in the lower limit for >250 us.

I am not sure how to control/eliminate the time gap (where its stuck at lower limit). Couldn't find anything relevant in the datasheet. Alternatively I have fixed the DRCTL pins to high in the CPLD, and just use the increment fields instead. This is what I got by combining the DRG (frequency) and RAM (amplitude).

Amplitude and frequency changes simultaneously at a defined interval.

~~Are there any interest for this CPLD patch?~~
Nvm, just enable load LRR @ I/O Update in CFR1. See the DRG usage in ARTIQ.

« Previous Page