Urukul AD9912 product id mismatch

steine01

I am upgrading from an ARTIQ 7 system to ARTIQ 9 using the same hardware components (master + satellite, TTL, DDS, DAC, Sampler). Previously, the software was running on Windows/Miniconda, now it runs on Windows/MSYS2 using the offline installer as a basis. The software version of artiq_master is ARTIQ v9.99646+4f326a9, the gateware is a self-built version using Vivado 2024.2 on a Linux system, based on the git hash 961551dd29 from the release-9 branch of https://git.m-labs.hk/M-Labs/artiq. The hardware description json files for the master and satellite did not change between the old and new gateware, except for the deletion of pll_n as mentioned in the release notes for ARTIQ-8.

Building and flashing works without error and I can also launch the dashboard using artiq_session from MSYS2. When I launch startup.py, which for now only initializes 1 AD9912 Urukul board on the master, I see that a connection is established on the serial monitor, but receive the following error:


root:Terminating with exception (ValueError: Urukul AD9912 product id mismatch)
Core Device Traceback:
Traceback (most recent call first):
  File "<artiq>/coredevice/ad9912.py", line 120, column 13, in ... artiq.coredevice.ad9912.AD9912.init<artiq.coredevice.ad9912.AD9912>(...)
    raise ValueError("Urukul AD9912 product id mismatch")
    ^
  File "<artiq>/coredevice/ad9912.py", line 120, in ... artiq.coredevice.ad9912.AD9912.init<artiq.coredevice.ad9912.AD9912>(...) (RA=+0xed4)
    raise ValueError("Urukul AD9912 product id mismatch")
  File "C:/Users/ybion443/src/YbSr/repository/startup.py", line 20, in artiq_worker_startup.Startup.run(..., ...) (RA=+0x174)
    self.urukul0_ch0.init()
ValueError(0): Urukul AD9912 product id mismatch

End of Core Device Traceback
Traceback (most recent call last):
  File "C:/Users/ybion443/MSYS2_ARTIQ/clang64/lib/python3.14/site-packages/artiq/master/worker_impl.py", line 378, in main
    exp_inst.run()
    ~~~~~~~~~~~~^^
  File "C:/Users/ybion443/MSYS2_ARTIQ/clang64/lib/python3.14/site-packages/artiq/language/core.py", line 54, in run_on_core
    return getattr(self, arg).run(run_on_core, ((self,) + k_args), k_kwargs)
           ~~~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "C:/Users/ybion443/MSYS2_ARTIQ/clang64/lib/python3.14/site-packages/artiq/coredevice/core.py", line 177, in run
    self._run_compiled(kernel_library, embedding_map, symbolizer, demangler)
    ~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "C:/Users/ybion443/MSYS2_ARTIQ/clang64/lib/python3.14/site-packages/artiq/coredevice/core.py", line 166, in _run_compiled
    self.comm.serve(embedding_map, symbolizer, demangler)
    ~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "C:/Users/ybion443/MSYS2_ARTIQ/clang64/lib/python3.14/site-packages/artiq/coredevice/comm_kernel.py", line 744, in serve
    self._serve_exception(embedding_map, symbolizer, demangler)
    ~~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "C:/Users/ybion443/MSYS2_ARTIQ/clang64/lib/python3.14/site-packages/artiq/coredevice/comm_kernel.py", line 726, in _serve_exception
    raise python_exn
ValueError: Urukul AD9912 product id mismatch

I checked the issues and the forum and saw that mixing AD9910 and AD9912 cards in the same rack currently causes some unspecified error (https://git.m-labs.hk/M-Labs/artiq/issues/1676, https://git.m-labs.hk/M-Labs/artiq/issues/1610) and tried the fix mentioned in this issue, adding a secondary CPLD class and changing the AD9912 CPLD entries accordingly. This produces a different error upon executing startup.py concerning a mismatch between two different CPLD definitions for the same object. The original error also persists for the device_db posted below, which removes every device except for the Urukul I would like to initialize.

How can I fix this error?

device_db.py


# Autogenerated for the ptb3master_kasliv1 variant
core_addr = "192.168.1.3"

device_db = {
    "core": {
        "type": "local",
        "module": "artiq.coredevice.core",
        "class": "Core",
        "arguments": {
            "host": core_addr,
            "ref_period": 1e-09,
            "analyzer_proxy": "core_analyzer",
            "target": "rv32ima",
            "satellite_cpu_targets": {}
        },
    },
    "core_log": {
        "type": "controller",
        "host": "::1",
        "port": 1068,
        "command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
    },
    "core_moninj": {
        "type": "controller",
        "host": "::1",
        "port_proxy": 1383,
        "port": 1384,
        "command": "aqctl_moninj_proxy --port-proxy {port_proxy} --port-control {port} --bind {bind} " + core_addr
    },
    "core_analyzer": {
        "type": "controller",
        "host": "::1",
        "port_proxy": 1385,
        "port": 1386,
        "command": "aqctl_coreanalyzer_proxy --port-proxy {port_proxy} --port-control {port} --bind {bind} " + core_addr
    },
    "core_cache": {
        "type": "local",
        "module": "artiq.coredevice.cache",
        "class": "CoreCache"
    },
    "core_dma": {
        "type": "local",
        "module": "artiq.coredevice.dma",
        "class": "CoreDMA"
    },
    

    "i2c_switch0": {
        "type": "local",
        "module": "artiq.coredevice.i2c",
        "class": "I2CSwitch",
        "arguments": {"address": 0xe0}
    },
    "i2c_switch1": {
        "type": "local",
        "module": "artiq.coredevice.i2c",
        "class": "I2CSwitch",
        "arguments": {"address": 0xe2}
    }
}


device_db["eeprom_urukul0"] = {
    "type": "local",
    "module": "artiq.coredevice.kasli_i2c",
    "class": "KasliEEPROM",
    "arguments": {
        "port": "EEM5",
        "busno": 0,
        "sw0_device": "i2c_switch0",
        "sw1_device": "i2c_switch1"}
    }
device_db["spi_urukul0"] = {
    "type": "local",
    "module": "artiq.coredevice.spi2",
    "class": "SPIMaster",
    "arguments": {"channel": 0x00001f}
}

device_db["ttl_urukul0_io_update"] = {
    "type": "local",
    "module": "artiq.coredevice.ttl",
    "class": "TTLOut",
    "arguments": {"channel": 0x000020}
}

device_db["ttl_urukul0_sw0"] = {
    "type": "local",
    "module": "artiq.coredevice.ttl",
    "class": "TTLOut",
    "arguments": {"channel": 0x000021}
}

device_db["ttl_urukul0_sw1"] = {
    "type": "local",
    "module": "artiq.coredevice.ttl",
    "class": "TTLOut",
    "arguments": {"channel": 0x000022}
}

device_db["ttl_urukul0_sw2"] = {
    "type": "local",
    "module": "artiq.coredevice.ttl",
    "class": "TTLOut",
    "arguments": {"channel": 0x000023}
}

device_db["ttl_urukul0_sw3"] = {
    "type": "local",
    "module": "artiq.coredevice.ttl",
    "class": "TTLOut",
    "arguments": {"channel": 0x000024}
}

device_db["urukul0_cpld"] = {
    "type": "local",
    "module": "artiq.coredevice.urukul",
    "class": "CPLD",
    "arguments": {
        "spi_device": "spi_urukul0",
        "sync_device": None,
        "io_update_device": "ttl_urukul0_io_update",
        "refclk": 100000000.0,
        "clk_sel": 1,
        "clk_div": 0,
        "proto_rev": 9
    }
}

device_db["urukul0_ch0"] = {
    "type": "local",
    "module": "artiq.coredevice.ad9912",
    "class": "AD9912",
    "arguments": {
        "pll_en": 1,
        "chip_select": 4,
        "cpld_device": "urukul0_cpld",
        "sw_device": "ttl_urukul0_sw0"
    }
}

device_db["urukul0_ch1"] = {
    "type": "local",
    "module": "artiq.coredevice.ad9912",
    "class": "AD9912",
    "arguments": {
        "pll_en": 1,
        "chip_select": 5,
        "cpld_device": "urukul0_cpld",
        "sw_device": "ttl_urukul0_sw1"
    }
}

device_db["urukul0_ch2"] = {
    "type": "local",
    "module": "artiq.coredevice.ad9912",
    "class": "AD9912",
    "arguments": {
        "pll_en": 1,
        "chip_select": 6,
        "cpld_device": "urukul0_cpld",
        "sw_device": "ttl_urukul0_sw2"
    }
}

device_db["urukul0_ch3"] = {
    "type": "local",
    "module": "artiq.coredevice.ad9912",
    "class": "AD9912",
    "arguments": {
        "pll_en": 1,
        "chip_select": 7,
        "cpld_device": "urukul0_cpld",
        "sw_device": "ttl_urukul0_sw3"
    }
}

startup.py

from artiq.experiment import *

class Startup(EnvExperiment):

    def build(self):
        self.setattr_device("core")
        
        self.setattr_device("urukul0_cpld")
        self.setattr_device("urukul0_ch0")
        self.setattr_device("urukul0_ch1")
        self.setattr_device("urukul0_ch2")
        self.setattr_device("urukul0_ch3")
        
    @kernel
    def run(self):
        self.core.reset()
       
        # DDS
        self.urukul0_cpld.init()
        self.urukul0_ch0.init()
        self.urukul0_ch1.init()
        self.urukul0_ch2.init()
        self.urukul0_ch3.init()
        
        self.core.wait_until_mu(now_mu())

ptb3master.json

{
    "_description": "PTB 4.43 Master with backplane adapter",
    "target": "kasli",
    "variant": "ptb3master",
    "hw_rev": "v1.1",
    "base": "master",
    "ext_ref_frequency": 100e6,
    "core_addr": "192.168.1.101",
    "vendor": "QUARTIQ",
    "peripherals": [
        {
            "type": "dio",
            "edge_counter": true,
            "ports": [0],
            "board": "DIO_SMA",
            "hw_rev": "v1.1",
            "bank_direction_low": "input",
            "bank_direction_high": "output"
        },
        {
            "type": "dio",
            "ports": [1],
            "board": "DIO_SMA",
            "hw_rev": "v1.1",
            "bank_direction_low": "output",
            "bank_direction_high": "output"
        },
        {
            "type": "dio",
            "ports": [2],
            "board": "DIO_SMA",
            "hw_rev": "v1.1",
            "bank_direction_low": "output",
            "bank_direction_high": "output"
        },
        {
            "type": "sampler",
            "ports": [3]
        },
        {
            "type": "urukul",
            "ports": [5, 4],
            "dds": "ad9912",
            "clk_sel": 1,
            "refclk": 100e6
        },
        {
            "type": "urukul",
            "ports": [7, 6],
            "dds": "ad9912",
            "clk_sel": 1,
            "refclk": 100e6
        },
        {
            "type": "urukul",
            "ports": [9, 8],
            "dds": "ad9912",
            "clk_sel": 1,
            "refclk": 100e6
        },
        {
            "type": "zotino",
            "ports": [10]
        },
        {
            "type": "zotino",
            "ports": [11]
        }
   ]
}

steine01

From reading the changes to the Urukul AD9912 source code (https://git.m-labs.hk/M-Labs/artiq/src/branch/release-9/artiq/coredevice/ad9912.py), I suspect that there is an incompatibility between our Urukul firmware (most likely proto_rev 8, but maybe even earlier?) and the one ARTIQ expects. If I change the proto_rev entry for the Urukul CPLD from 9 to 8, I do not get the product ID mismatch anymore, but I always get an RTIO Underflow after self.urukul0_cpld.init() of ~ 10000 mu (~ 10 µs), no matter how much delay I add.

occheung

steine01 If I change the proto_rev entry for the Urukul CPLD from 9 to 8, I do not get the product ID mismatch anymore

proto_rev is tied to your Urukul firmware.
Given that your system was running ARTIQ-7, your Urukul probably use a proto_rev 8 firmware (unless reflashed).
I am surprised that the kernel does not complain about proto_rev mismatch though when initializing the CPLD.

steine01 I can execute startup successfully, if I add additional delay in two places in the initialization routine of the AD9912

Calling self.core.break_realtime() before every init() doesn't help?

steine01

Using proto_rev 8 for all Urukul CPLDs, I can execute startup successfully, if I add additional delay in two places in the initialization routine of the AD9912.

coredevice/ad9912.py

@kernel
    def init(self):
        """Initialize and configure the DDS.

        Sets up SPI mode, confirms chip presence, powers down unused blocks,
        and configures the PLL. Does not wait for PLL lock. Uses the
        ``IO_UPDATE`` signal multiple times.
        """
        # SPI mode
        self.write(AD9912_SER_CONF, 0x99, length=1)
        self.io_update.pulse(2 * us)
        # Verify chip ID and presence
        prodid = self.read(AD9912_PRODIDH, length=2)
        if (prodid != 0x1982) and (prodid != 0x1902):
            raise ValueError("Urukul AD9912 product id mismatch")
        #delay(50 * us)
        delay(85 * us) # Added by steine01
        # HSTL power down, CMOS power down
        pwrcntrl1 = 0x80 | ((~self.pll_en & 1) << 4)
        self.write(AD9912_PWRCNTRL1, pwrcntrl1, length=1)
        self.io_update.pulse(2 * us)
        delay(85 * us) # Added by steine01
        if self.pll_en:
            self.write(AD9912_N_DIV, self.pll_n // 2 - 2, length=1)
            self.io_update.pulse(2 * us)
            # I_cp = 375 µA, VCO high range
            if self.cpld.refclk < 11e6:
                # enable SYSCLK PLL Doubler
                self.write(AD9912_PLLCFG, 0b00001101, length=1)
            else:
                self.write(AD9912_PLLCFG, 0b00000101, length=1)
            self.io_update.pulse(2 * us)
        delay(1 * ms)

steine01

occheung I never reflashed the Urukul. Since I build the firmware on my own from the repository, does proto_rev also have to be specified in the .json file for firmware compilation? While the DDS can be used with standard experiments, I don't see it (or any other DDS) in the MonInj list (TTL and DAC are available) and have the suspicion that this might be connected.

No, a self.core.break_realtime() before and after each init() has no effect on the RTIOUnderflow. This is the error when using the original source code for ad9912.py, with self.core.break_realtime() added before and after each init:

root:Terminating with exception (RTIOUnderflow: RTIO underflow at channel 0x0020:unknown, 514880826987408 mu, slack -9624 mu)
Core Device Traceback:
Traceback (most recent call first):
  File "ksupport/rtio.rs", line 69, column 14, in (Rust function)
    <unknown>
                 ^
  File "<artiq>/coredevice/ad9912.py", line 125, in ... artiq.coredevice.ad9912.AD9912.init<artiq.coredevice.ad9912.AD9912>(...) (RA=+0xc1c)
    self.io_update.pulse(2 * us)
  File "C:/Users/ybion443/src/YbSr/repository/startup_test.py", line 25, in artiq_worker_startup_test.StartupTest.run(..., ...) (RA=+0x184)
    self.urukul0_ch0.init()
artiq.coredevice.exceptions.RTIOUnderflow(0): RTIO underflow at channel 0x0020:unknown, 514880826987408 mu, slack -9624 mu

End of Core Device Traceback
Traceback (most recent call last):
  File "C:/Users/ybion443/MSYS2_ARTIQ/clang64/lib/python3.14/site-packages/artiq/master/worker_impl.py", line 378, in main
    exp_inst.run()
    ~~~~~~~~~~~~^^
  File "C:/Users/ybion443/MSYS2_ARTIQ/clang64/lib/python3.14/site-packages/artiq/language/core.py", line 54, in run_on_core
    return getattr(self, arg).run(run_on_core, ((self,) + k_args), k_kwargs)
           ~~~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "C:/Users/ybion443/MSYS2_ARTIQ/clang64/lib/python3.14/site-packages/artiq/coredevice/core.py", line 177, in run
    self._run_compiled(kernel_library, embedding_map, symbolizer, demangler)
    ~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "C:/Users/ybion443/MSYS2_ARTIQ/clang64/lib/python3.14/site-packages/artiq/coredevice/core.py", line 166, in _run_compiled
    self.comm.serve(embedding_map, symbolizer, demangler)
    ~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "C:/Users/ybion443/MSYS2_ARTIQ/clang64/lib/python3.14/site-packages/artiq/coredevice/comm_kernel.py", line 744, in serve
    self._serve_exception(embedding_map, symbolizer, demangler)
    ~~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "C:/Users/ybion443/MSYS2_ARTIQ/clang64/lib/python3.14/site-packages/artiq/coredevice/comm_kernel.py", line 726, in _serve_exception
    raise python_exn
artiq.coredevice.exceptions.RTIOUnderflow: RTIO underflow at channel 0x0020:unknown, 514880826987408 mu, slack -9624 mu

startup_test.py

import sys

from artiq.experiment import *


class StartupTest(EnvExperiment):

    def build(self):
        self.setattr_device("core")

        self.setattr_device("urukul0_cpld")
        self.setattr_device("urukul0_ch0")
        self.setattr_device("urukul0_ch1")
        self.setattr_device("urukul0_ch2")
        self.setattr_device("urukul0_ch3")

    @kernel
    def run(self):
        self.core.reset()
        
        # DDS
        self.core.break_realtime()
        self.urukul0_cpld.init()
        self.core.break_realtime()
        self.urukul0_ch0.init()
        self.core.break_realtime()
        self.urukul0_ch1.init()
        self.core.break_realtime()
        self.urukul0_ch2.init()
        self.core.break_realtime()
        self.urukul0_ch3.init()
        self.core.break_realtime()

        self.core.wait_until_mu(now_mu())

steine01

Short update, specifying proto_rev: 8 during firmware compilation and reflashing the Kasli had no effect on either the RTIOUnderflow or the absence of the DDS in the MonInj dashboard.

occheung

There are some Urukul clocking configuration restructuring on ARTIQ-9, which probably crashes the GUI generation for Urukuls, causing them to not show up on MonInj.

Thank you for reporting. Will get back to you once resolved.