Hi all,
I'm a graduate student starting a thesis project on building a low-cost, open-source FPGA-based auxiliary real-time controller to complement an existing ARTIQ/Sinara setup, and I wanted to check with the community before committing to the design.
Has anyone integrated a Red Pitaya (or a similar low-cost Zynq-based board) as a gateware-native fast-feedback coprocessor alongside ARTIQ — i.e., a satellite device where the real-time decision logic (e.g. threshold-based state discrimination, conditional triggering) runs entirely in the PL fabric, without involving the core device's kernel/CPU at all?
I'm aware of:
- The NDSP mechanism for non-realtime devices (RPC-based configuration)
- The discussion in Lam et al. 2021 (arXiv:2111.15290) about ACP-based kernel-gateware coupling on Zynq, and their mention of "fast paths through the gateware without involving the PS" as future work
- The Oxford Ion Trap Group's entangler-core project as a bespoke example of gateware-level real-time logic alongside ARTIQ
But I haven't found a documented, open, general-purpose implementation of this specific pattern (external low-cost board, PL-only decision logic, formally integrated via NDSP + a hardware trigger/shared clock for real-time sync) — on Red Pitaya or otherwise.
Before I invest 8 months of thesis work into this, I'd really appreciate it if anyone could point me to:
- Any existing project, internal lab tool, or unpublished work that does something similar
- Whether this specific gap has effectively been closed by more recent ARTIQ/Sinara developments that I might have missed
- Any reasons this approach might be a bad idea architecturally that I should know about upfront
Thanks in advance — happy to share results back with the community once the project is underway, regardless of what I find.