Hello,
We are observing an unexpected periodic fluctuation in photon counts when the absolute timing of a fixed-duration TTL input gate is shifted relative to the 8 ns RTIO coarse-clock period.
Our APD output is connected to a Sinara TTL input, and we count the rising edges of the APD TTL pulses. The photon-detection gate is shorter than 1 µs, typically around 200 ns, and its duration is kept fixed. Photon counts are accumulated over many experimental repetitions.
We first observed this artifact during a Rabi measurement. As the Rabi pulse duration is swept, the subsequent detection gate is shifted in time. Therefore, the detection-gate width remains constant, but its absolute start and end timestamps change with the scanned Rabi duration.
The measured photon count shows a periodic dependence on this timing shift. For example, scan points aligned to an integer multiple of the 8 ns coarse RTIO period, such as 160 ns, give stable photon counts. At non-aligned points, such as 163 ns, we observe an unintended periodic fluctuation with an amplitude of approximately 10%.
Restricting the scanned timing values to integer multiples of 8 ns appears to remove the fluctuation. We are therefore currently using this as a workaround, but we do not understand the underlying mechanism.
Our current setup is approximately as follows:
- ARTIQ version: 7, although we will verify the exact version
- APD output pulse width: approximately 28 ns
- APD dead time: approximately 35 ns
- Photon-detection gate width: approximately 200 ns and fixed
Only the absolute gate timing, including the gate-end timestamp, changes as the preceding Rabi pulse duration is swept
Because the APD pulse width and dead time are both significantly longer than one 8 ns coarse RTIO cycle, we do not expect multiple APD rising edges within a single coarse cycle to be the direct cause.
Could this behavior be caused by one of the following?
- quantization of the TTL input gate opening or closing to the coarse RTIO clock;
- truncation or alignment of the gate-end timestamp to an 8 ns boundary;
- phase walking between the shifted detection gate and the RTIO coarse clock;
- interaction between fine input timestamps and coarse gate-control timing;
- the implementation of the TTL input PHY or edge-counting logic.
Is a fixed TTL input gate expected to produce identical counts when its absolute timing is shifted by increments smaller than one coarse RTIO period? Alternatively, should the entire experimental sequence and the input-gate boundaries always be aligned to multiples of the coarse RTIO period?
We can provide a minimal ARTIQ example, the exact ARTIQ and gateware versions, the Sinara hardware configuration, and additional APD specifications if needed.
Any help in understanding this behavior would be greatly appreciated.