We wanted to install a new urukul card into our old ARTIQ system which was still running on ARTIQ 8. The old urukul was on v1.5.6 whereas the new one is on v1.6.0. When we installed this card and reflashed the FPGA again, we were getting an error with proto_rev mismatch
artiq_sinara_tester -o urukuls
****** Sinara system tester ******
*** Testing Urukul DDSes.
urukul0_cpld: initializing CPLD...
Traceback (most recent call last):
File "<frozen runpy>", line 203, in _run_module_as_main
File "<frozen runpy>", line 88, in _run_code
File "C:/msys64/clang64/bin/artiq_sinara_tester.exe/__main__.py", line 7, in <module>
sys.exit(main())
~~~~^^
File "C:/msys64/clang64/lib/python3.14/site-packages/artiq/frontend/artiq_sinara_tester.py", line 1352, in main
experiment.run(tests)
~~~~~~~~~~~~~~^^^^^^^
File "C:/msys64/clang64/lib/python3.14/site-packages/artiq/frontend/artiq_sinara_tester.py", line 1303, in run
getattr(self, f"test_{name}")()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^^
File "C:/msys64/clang64/lib/python3.14/site-packages/artiq/frontend/artiq_sinara_tester.py", line 335, in test_urukuls
self.init_urukul(cpld)
~~~~~~~~~~~~~~~~^^^^^^
File "C:/msys64/clang64/lib/python3.14/site-packages/artiq/language/core.py", line 54, in run_on_core
return getattr(self, arg).run(run_on_core, ((self,) + k_args), k_kwargs)
~~~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "C:/msys64/clang64/lib/python3.14/site-packages/artiq/coredevice/core.py", line 177, in run
self._run_compiled(kernel_library, embedding_map, symbolizer, demangler)
~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "C:/msys64/clang64/lib/python3.14/site-packages/artiq/coredevice/core.py", line 166, in _run_compiled
self.comm.serve(embedding_map, symbolizer, demangler)
~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "C:/msys64/clang64/lib/python3.14/site-packages/artiq/coredevice/comm_kernel.py", line 744, in serve
self._serve_exception(embedding_map, symbolizer, demangler)
~~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "C:/msys64/clang64/lib/python3.14/site-packages/artiq/coredevice/comm_kernel.py", line 726, in _serve_exception
raise python_exn
ValueError: Urukul proto_rev mismatch
Since we started on ARTIQ 8, the proto_rev was set to 8 initially, since then we tried setting proto_rev to 9 and reflashing, upgrading to ARTIQ 9 and reflashing and even using proto_rev 8 for ARTIQ 9, but all of them result in the same error. I also checked that the cards are connected in the same order mentioned in the json file as well. Is it possible that the older dds only works for proto_rev 8 but the newer dds needs proto_rev 9? I did not spot anything out of the ordinary in the UART logs either
__________ __
/ ___/__ / / /
\__ \ / / / /
___/ / / /__/ /___
/____/ /____/_____/
(C) 2020-2022 M-Labs
[ 0.019987s] INFO(szl): Simple Zynq Loader starting...
[ 0.025194s] DEBUG(libboard_zynq::clocks::source): Set ARM_PLL to 2000000000 Hz
[ 0.007039s] DEBUG(libboard_zynq::clocks::source): Set IO_PLL to 1000000000 Hz
[ 0.016258s] DEBUG(libboard_zynq::clocks::source): Set DDR_PLL to 1066666666 Hz
[ 0.023607s] DEBUG(libboard_zynq::ddr): DDR 3x/2x clocks: 533333328/355555552
[ 0.030776s] DEBUG(libboard_zynq::ddr): DDR DCI clock: 10062892 Hz (divisors=2*53)
[ 0.042000s] DEBUG(libboard_zynq::sdio): Reset SDIO!
[ 0.046946s] DEBUG(libboard_zynq::sdio): Changing clock frequency to 400000
[ 0.053894s] INFO(szl): Card inserted. Mounting file system.
[ 0.083719s] DEBUG(libboard_zynq::sdio): Changing clock frequency to 25000000
[ 0.090772s] DEBUG(libboard_zynq::sdio::sd_card): Getting bus width
[ 0.098989s] DEBUG(libboard_zynq::sdio::sd_card): 4 bit support
[ 0.104885s] DEBUG(libboard_zynq::sdio::sd_card): Changing bus width
[ 0.113001s] DEBUG(libboard_zynq::sdio): Set block size to 512
[ 0.121185s] DEBUG(libconfig::sd_reader): Partition ID: C
[ 0.127295s] INFO(szl): Loading gateware
[ 0.131520s] DEBUG(libconfig::bootgen): Partition header pointer = C80
[ 0.138223s] DEBUG(libconfig::bootgen): Unencrypted length = 96934
[ 0.144379s] DEBUG(libconfig::bootgen): Partition start address: B630
[ 0.410862s] DEBUG(libboard_zynq::devc): Invalidate DCache for bitstream buffer
[ 0.423080s] DEBUG(libboard_zynq::devc): Init preload FPGA
[ 0.428545s] DEBUG(libboard_zynq::devc): Toggling PROG_B
[ 0.453332s] DEBUG(libboard_zynq::devc): Waiting for done
[ 0.458709s] DEBUG(libboard_zynq::devc): Init postload FPGA
[ 0.464263s] INFO(szl): Loading runtime
[ 0.470051s] DEBUG(libconfig::bootgen): Partition header pointer = C80
[ 0.476681s] DEBUG(libconfig::bootgen): Unencrypted length = B064
[ 0.482753s] DEBUG(libconfig::bootgen): Unencrypted length = 2F9CA
[ 0.488914s] DEBUG(libconfig::bootgen): Partition start address: A1F70
[ 0.583265s] INFO(szl): Preparing for runtime execution
[ 0.588825s] INFO(szl): executing payload
[ 0.000067s] INFO(runtime): NAR3/Zynq7000 starting...
[ 0.005238s] INFO(runtime): gateware ident: 8+c63604d0;nus6
[ 0.016067s] INFO(libboard_zynq::i2c): PCA9548 detected
[ 0.176236s] INFO(runtime::rtio_clocking): using internal 125MHz RTIO clock
[ 0.566979s] INFO(libboard_artiq::si5324): waiting for Si5324 lock...
[ 5.961403s] INFO(libboard_artiq::si5324): ...locked
[ 5.966615s] INFO(runtime::rtio_clocking): Switching SYS clocks...
[ 6.022988s] INFO(runtime::rtio_clocking): SYS CLK switched successfully
[ 6.029762s] INFO(runtime::rtio_clocking): SYS PLL locked
[ 6.040429s] INFO(libboard_zynq::i2c): PCA9548 detected
[ 6.076496s] INFO(runtime::comms): network addresses: MAC=fc-0f-e7-0e-c6-a8 IPv4=192.168.108.10 IPv6-LL=fe80::fe0f:e7ff:fe0e:c6a8 IPv6: no configured address
[ 6.104537s] INFO(runtime::rtio_mgt): SED spreading disabled by default
[ 10.113083s] INFO(libboard_zynq::eth): eth: got Link { speed: S1000, duplex: Full }
[ 11.177027s] INFO(ksupport::kernel::core1): kernel starting
[ 11.182684s] INFO(ksupport::kernel::core1): kernel finished
[ 11.368850s] INFO(ksupport::kernel::core1): kernel starting
[ 11.374651s] INFO(ksupport::kernel::core1): kernel finished
[ 11.537052s] INFO(ksupport::kernel::core1): kernel starting
[ 11.543387s] INFO(ksupport::kernel::core1): kernel finished
[ 11.723527s] INFO(ksupport::kernel::core1): kernel starting
[ 11.800371s] INFO(runtime::comms): peer closed connection
[ 19.308242s] INFO(runtime::mgmt): received connection
[ 48.677260s] INFO(runtime::mgmt): received connection
[ 48.682650s] INFO(runtime::mgmt): rebooting
__________ __
/ ___/__ / / /
\__ \ / / / /
___/ / / /__/ /___
/____/ /____/_____/
(C) 2020-2022 M-Labs
[ 0.019994s] INFO(szl): Simple Zynq Loader starting...
[ 0.025201s] DEBUG(libboard_zynq::clocks::source): Set ARM_PLL to 2000000000 Hz
[ 0.007040s] DEBUG(libboard_zynq::clocks::source): Set IO_PLL to 1000000000 Hz
[ 0.016259s] DEBUG(libboard_zynq::clocks::source): Set DDR_PLL to 1066666666 Hz
[ 0.023608s] DEBUG(libboard_zynq::ddr): DDR 3x/2x clocks: 533333328/355555552
[ 0.030777s] DEBUG(libboard_zynq::ddr): DDR DCI clock: 10062892 Hz (divisors=2*53)
[ 0.042000s] DEBUG(libboard_zynq::sdio): Reset SDIO!
[ 0.046947s] DEBUG(libboard_zynq::sdio): Changing clock frequency to 400000
[ 0.053895s] INFO(szl): Card inserted. Mounting file system.
[ 0.083164s] DEBUG(libboard_zynq::sdio): Changing clock frequency to 25000000
[ 0.090295s] DEBUG(libboard_zynq::sdio::sd_card): Getting bus width
[ 0.098455s] DEBUG(libboard_zynq::sdio::sd_card): 4 bit support
[ 0.104356s] DEBUG(libboard_zynq::sdio::sd_card): Changing bus width
[ 0.112001s] DEBUG(libboard_zynq::sdio): Set block size to 512
[ 0.120192s] DEBUG(libconfig::sd_reader): Partition ID: C
[ 0.126321s] INFO(szl): Loading gateware
[ 0.130571s] DEBUG(libconfig::bootgen): Partition header pointer = C80
[ 0.137205s] DEBUG(libconfig::bootgen): Unencrypted length = 96934
[ 0.143364s] DEBUG(libconfig::bootgen): Partition start address: B630
[ 0.407636s] DEBUG(libboard_zynq::devc): Invalidate DCache for bitstream buffer
[ 0.419783s] DEBUG(libboard_zynq::devc): Init preload FPGA
[ 0.425248s] DEBUG(libboard_zynq::devc): Toggling PROG_B
[ 0.450114s] DEBUG(libboard_zynq::devc): Waiting for done
[ 0.455490s] DEBUG(libboard_zynq::devc): Init postload FPGA
[ 0.461044s] INFO(szl): Loading runtime
[ 0.466747s] DEBUG(libconfig::bootgen): Partition header pointer = C80
[ 0.473459s] DEBUG(libconfig::bootgen): Unencrypted length = B064
[ 0.479534s] DEBUG(libconfig::bootgen): Unencrypted length = 2F9CA
[ 0.485695s] DEBUG(libconfig::bootgen): Partition start address: A1F70
[ 0.578891s] INFO(szl): Preparing for runtime execution
[ 0.584529s] INFO(szl): executing payload
[ 0.000067s] INFO(runtime): NAR3/Zynq7000 starting...
[ 0.005238s] INFO(runtime): gateware ident: 8+c63604d0;nus6
[ 0.016073s] INFO(libboard_zynq::i2c): PCA9548 detected
[ 0.176282s] INFO(runtime::rtio_clocking): using internal 125MHz RTIO clock
[ 0.566947s] INFO(libboard_artiq::si5324): waiting for Si5324 lock...
[ 5.961929s] INFO(libboard_artiq::si5324): ...locked
[ 5.967136s] INFO(runtime::rtio_clocking): Switching SYS clocks...
[ 6.023989s] INFO(runtime::rtio_clocking): SYS CLK switched successfully
[ 6.030760s] INFO(runtime::rtio_clocking): SYS PLL locked
[ 6.041428s] INFO(libboard_zynq::i2c): PCA9548 detected
[ 6.077513s] INFO(runtime::comms): network addresses: MAC=fc-0f-e7-0e-c6-a8 IPv4=192.168.108.10 IPv6-LL=fe80::fe0f:e7ff:fe0e:c6a8 IPv6: no configured address
[ 6.105537s] INFO(runtime::rtio_mgt): SED spreading disabled by default
[ 10.114082s] INFO(libboard_zynq::eth): eth: got Link { speed: S1000, duplex: Full }
[ 11.329416s] INFO(ksupport::kernel::core1): kernel starting
[ 11.335079s] INFO(ksupport::kernel::core1): kernel finished
[ 11.520054s] INFO(ksupport::kernel::core1): kernel starting
[ 11.525857s] INFO(ksupport::kernel::core1): kernel finished
[ 11.691648s] INFO(ksupport::kernel::core1): kernel starting
[ 11.697908s] INFO(ksupport::kernel::core1): kernel finished
[ 11.878199s] INFO(ksupport::kernel::core1): kernel starting
[ 11.955195s] INFO(runtime::comms): peer closed connection