Thanks for your help. Now that I'm back in the lab and can actually try this I've run into some issues.
Is it possible to run the whole system with an external clock at 10 MHz so that the clocker's front panel outputs give 10MHz?
I tried this. I plugged a Rb referenced 10MHz signal (attenuated to 1.8v) into the clk SMA on the front of the kasli and set the rtio_clock setting to 'e' with artiq_coremgmt. Then I changed pll_n, pll_vco, and clk_div in our device_db apprpriately. Now I'm getting the error "PLL lock timeout". Should I try messing with the charge pump settings or something?
Alternatively, but less ideally for us, is there a way to feed 10MHz in and then have the SI5324 output 125 MHz? I was looking for some sort of artiq_coremgmt command to accomplish this but I couldn't find anything. This file the closest thing I could find but I'm not sure how to enable it.