Hi
I am trying to run a zotino ramp and urukul (ad9910) ramp in parallel in a much larger script which has only a single kernel with all the necessary functions. Please see the code attached below. For both of the ramps it is a very simple implementation of writing the frequency or voltage to the relevant channels and having a delay in between these writes. However I am getting an underflow error which directly related to this section of the code. Does anyone have any experience in implementing parallel ramps in this manner? I would appreciate any advice.
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with parallel:
if self.list_of_amplitude_modulation_selector[i] == 1:
self.DDS_ad9910_channel0.set_cfr1(ram_enable=0)
self.DDS_ad9910_channel0.cpld.io_update.pulse(100*ns)
self.DDS_ad9910_channel0.set_att(self.list_ad9910_channel0_atten[i])
self.DDS_ad9910_channel0.set(self.list_ad9910_channel0_freq[i] * MHz, amplitude = 1.0)
self.DDS_ad9910_channel3.set_cfr1(ram_enable=0)
self.DDS_ad9910_channel3.cpld.io_update.pulse(100*ns)
self.DDS_ad9910_channel3.set_att(self.list_ad9910_channel3_atten[i])
self.DDS_ad9910_channel3.set(self.list_ad9910_channel3_freq[i] * MHz, amplitude = 1.0)
self.DDS_ad9910_channel2.set_cfr1(ram_enable=0)
self.DDS_ad9910_channel2.cpld.io_update.pulse(100*ns)
self.DDS_ad9910_channel2.set_att(self.list_ad9910_channel2_atten[i])
self.DDS_ad9910_channel2.set(self.list_ad9910_channel2_freq[i] * MHz, amplitude = 1.0)
self.DDS_ad9910_channel1.set_cfr1(ram_enable=0)
self.DDS_ad9910_channel1.cpld.io_update.pulse(100*ns)
self.DDS_ad9910_channel1.set_att(self.list_ad9910_channel1_atten[i])
self.DDS_ad9910_channel1.set(self.list_ad9910_channel1_freq[i] * MHz, amplitude = 1.0)
kk4 = 0
for entry in self.list_of_combined_amplitude_coloumn[i]:
if self.array_channel_time[i][kk4][0] == 3.0:
self.DDS_ad9910_channel3.set(self.list_ad9910_channel3_freq[i] * MHz, amplitude = self.array_amplitude_time[i][kk4][0])
if self.array_channel_time[i][kk4][0] == 2.0:
self.DDS_ad9910_channel2.set(self.list_ad9910_channel2_freq[i] * MHz, amplitude = self.array_amplitude_time[i][kk4][0])
if self.array_channel_time[i][kk4][0] == 1.0:
self.DDS_ad9910_channel1.set(self.list_ad9910_channel1_freq[i] * MHz, amplitude = self.array_amplitude_time[i][kk4][0])
if self.array_channel_time[i][kk4][0] == 0.0:
self.DDS_ad9910_channel0.set(self.list_ad9910_channel0_freq[i] * MHz, amplitude = self.array_amplitude_time[i][kk4][0])
delay(self.array_channel_time[i][kk4][1] * ns)
kk4 = kk4 + 1
if self.list_of_zotino_ramp_selector[i] == 1:
MM4 = 0
for entry2 in self.final_channel_list[i]:
self.zotino0.write_dac(self.final_channel_list[i][MM4], self.final_voltage_list[i][MM4])
self.zotino0.load()
delay(self.final_time_list[i][MM4] * ns)
MM4 = MM4 + 1`