I am trying to playback a DMA handle and run the TTL edge counter function gate_rising in parallel, and even though the script runs without errors, the red lights on the AD9910 urukul board switches on alongside the existing green lights.
I have looked at the coremgmt log and this is related to the RTIO sequence errors. The sequence errors involve two channels, channel 29 and 0.
One solution is to increase the SED lanes but by how much can I safely increase the SED lanes in sed/core.py given that there is a corresponding increase in the FPGA usage?
self.ttlcounter_0.gate_rising((self.list_t_duration[i]*0.2) * ns)