Mirny + artiq_sinara_tester: "MUXOUT not low"

FabianS

Hi everyone,
I am trying to get the Mirny up and running. It seems like it is detected by artiq, but the artiq_sinara_tester (and my own programms as wel) fail with "ValueError: MUXOUT not low".
I guess the MUX is set to lock detect output, so he is not getting a lock. From the hardware point of view everything seems ok. I am feeding the 125 MHz clock from Kasli into the Mirny MMCX clock input, and the device_db.json has both values for that set.
I am a bit lost here. Any idea is welcome. My current guess would be that the hardware is broken somehow, as I would expect the default tests to pass without any issues on a new device.
Is there a way to read/write the registers of the ADF** devices? So I can check what is actually going on. And I will probably also need this feature later.

rjo

Did you try with the reference artiq_sinara_tester as well?
Always useful to send the actual device_db and script you are using. Prevents a lot of speculation and allows identifying issues.
The chip doesn't allow reading registers.

FabianS

I am not sure what you mean with the first question. Yes, I used artiq_sinara_tester.
However, after I started the system this morning, everything was working as expected. I guess a case of "Have you tried turning it off an on again?".
But my other question stays: Is there a way to write the registers of the PLL directly? It seems that it is not configured for deterministic operation by the default functions. I get random phases compared to the 125 MHz reference when using exact integer multiples.

FabianS

OK, figured it out myself.
Although there is no function to do that, you can just set the regiserts in
self.mirny0_ch0.regs[n] = 0x12345678
and call
self.mirny0_ch0.sync()
to push the registers into the PLL.
Anything wrong with that method?

rjo

Sorry. I overread your infor about having tried artiq_sinara_tester.
I can imagine that the way the MUXOUT is used to detect presence of a PLL chip may fail e.g. when the PLL chip has lost SPI synchronization due to improper commands. But even then the fact that it can't toggle MUXOUT correctly indicates a non-responsive chip. And we've seen with other chips that the only thing that helps then is a power cycle.
Writing should work fine. Either follow the lines of set_frequency() with setting self.regs and then sync() or write registers directly using write().

FabianS

Thanks for the info.
But I think there is still some strange problem with the detection of the PLL.
When initializing the CPLD and the PLL with their init() functions, I can run that script as often as I want and everything is ok:
`from artiq.experiment import *
from artiq.coredevice.mirny import *

class Mirny(EnvExperiment):
def build(self):
self.setattr_device("core")
#print(self.get_device_db())
self.setattr_device("mirny0_cpld")
self.setattr_device("mirny0_ch0")

def run(self):
    self.do()

@kernel
def do(self):
    self.core.reset()
    self.core.break_realtime()
    mirny = self.mirny0_ch0

    delay(10*ms)
    mirny.cpld.init()

    delay(10*ms)
    mirny.init()

    mirny.set_att_mu(255)
    mirny.sw.on()
    mirny.set_frequency(125e6)

    delay(10*ms)`

But when I additionally program the registers manually, it fails randomly, about every second try, with "MUXOUT not high":
`from artiq.experiment import *
from artiq.coredevice.mirny import *

class Mirny(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("mirny0_cpld")
self.setattr_device("mirny0_ch0")

def run(self):
    self.do()

@kernel
def do(self):
    self.core.reset()
    self.core.break_realtime()
    mirny = self.mirny0_ch0

    delay(10*ms)
    mirny.cpld.init()

    delay(10*ms)
    mirny.init()

    mirny.set_att_mu(255)
    mirny.sw.on()
    mirny.set_frequency(125e6)

    delay(10*ms)
    mirny.regs[0] = 0x200200
    mirny.regs[1] = 0x1
    mirny.regs[2] = 0x12
    mirny.regs[3] = 0x20000003
    mirny.regs[4] = 0x30100984
    mirny.regs[5] = 0x800025
    mirny.regs[6] = 0x34A3C0F6
    mirny.regs[7] = 0x12000067
    mirny.regs[8] = 0x102D0428
    mirny.regs[9] = 0x201FCC9
    mirny.regs[10] = 0xC002BA
    mirny.regs[11] = 0x61300B
    mirny.regs[12] = 0xFFFF041C
    mirny.sync()`

rjo

This sounds like a problem with the PLL chip functionality and/or the registers values you write.