Platform: Kasli
Target: Modified Tester (see below)
Origin commit: 6644903 from Nov 6th
Problem:
Trying to get access to CSR from ARTIQ kernel to develop device driver.
What I did:
- Created a simple module with only two CSRs:
class TestModule(Module, AutoCSR):
def __init__(self):
self.user_led_1 = CSRStorage()
self.user_led_2 = CSRStorage()
- Added this module to Kasli Tester target and made it drive two user LEDs:
...
StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
self.submodules.test_module = TestModule()
self.csr_devices.append("test_module")
self.comb += [
self.platform.request("user_led", 1).eq(self.test_module.user_led_1.storage),
self.platform.request("user_led", 2).eq(self.test_module.user_led_2.storage),
]
self.config["SI5324_AS_SYNTHESIZER"] = None
...
- Added API declarations to
firmware/ksupport/api.rs:
api!(user_led_1_read = ::csr::test_module::user_led_1_read),
api!(user_led_1_write = ::csr::test_module::user_led_1_write),
api!(user_led_2_read = ::csr::test_module::user_led_2_read),
api!(user_led_2_write = ::csr::test_module::user_led_2_write),
- Created a simple experiment:
from artiq.experiment import *
from artiq.language.core import syscall, kernel
@syscall
def user_led_1_read() -> TInt32:
raise NotImplementedError("syscall not simulated")
@syscall
def user_led_1_write(d: TInt32) -> TNone:
raise NotImplementedError("syscall not simulated")
@syscall
def user_led_2_read() -> TInt32:
raise NotImplementedError("syscall not simulated")
@syscall
def user_led_2_write(d: TInt32) -> TNone:
raise NotImplementedError("syscall not simulated")
class LedTester(EnvExperiment):
def build(self):
self.setattr_device("core")
@kernel
def run(self):
user_led_1_write(1)
user_led_2_write(1)
- I run
artiq_run and the following could be observed on the serial output:
__ __ _ ____ ____
| \/ (_) ___| ___ / ___|
| |\/| | \___ \ / _ \| |
| | | | |___) | (_) | |___
|_| |_|_|____/ \___/ \____|
MiSoC Bootloader
Copyright (c) 2017-2019 M-Labs Limited
Bootloader CRC passed
Gateware ident 5.0.dev+700.g66449038.dirty;tester
Initializing SDRAM...
Read leveling scan:
Module 1:
00000000000111111111110000000000
Module 0:
00000000000111111111111000000000
Read leveling: 16+-5 16+-6 done
SDRAM initialized
Memory test passed
Booting from flash...
Starting firmware.
[ 0.000009s] INFO(runtime): ARTIQ runtime starting...
[ 0.003932s] INFO(runtime): software ident 5.0.dev+700.g66449038.dirty;tester
[ 0.011172s] INFO(runtime): gateware ident 5.0.dev+700.g66449038.dirty;tester
[ 0.018435s] INFO(runtime): log level set to INFO by default
[ 0.024143s] INFO(runtime): UART log level set to INFO by default
[ 0.030528s] INFO(runtime::rtio_clocking): using internal RTIO clock (by default)
[ 0.315085s] INFO(board_artiq::si5324): waiting for Si5324 lock...
[ 4.772577s] INFO(board_artiq::si5324): ...locked
[ 4.776547s] INFO(runtime): network addresses: MAC=42-13-3c-bc-a2-21 IPv4=10.100.0.97 IPv6-LL=fe80::s
[ 4.791434s] INFO(runtime::mgmt): management interface active
[ 4.805983s] INFO(runtime::session): accepting network sessions
[ 4.821473s] INFO(runtime::session): running startup kernel
[ 4.826003s] INFO(runtime::session): no startup kernel found
[ 4.831764s] INFO(runtime::session): no connection, starting idle kernel
[ 4.838647s] INFO(runtime::session): no idle kernel found
[ 1230.787159s] INFO(runtime::session): new connection from 10.100.0.14:36548
panic at src/libcore/slice/mod.rs:1965:5index 4294967295 out of range for slice of length 4092
backtrace for software version 5.0.dev+700.g66449038.dirty;tester:
0x40041894
0x40021148
0x400218b4
0x4002463c
0x40021cf4
halting.
use `artiq_coremgmt config write -s panic_reset 1` to restart instead
Question:
I must be doing something wrong. What is the recommended way of accessing CSR from ARTIQ kernel?