I'm using the code below to ramp the amplitude of dds. The amplitude is increasing from 0 to 1. But the output amplitude is actually decreasing from 1 to 0. It seems the ram is played in the reverse direction from the end address to the start address. Do I take anything wrong?
from artiq.experiment import *
from artiq.coredevice import ad9910
class TestDdsAmpRamp(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("ttl5")
self.u0 = self.get_device("urukul0_ch0")
@kernel
def run(self):
# prepare ram data
n = 7
data = [0] * (1 << n)
amp = [0.0] * len(data)
for i in range(len(data)):
amp[i] = (i + 1) / len(data)
self.u0.amplitude_to_ram(amp, data)
self.core.reset()
self.u0.cpld.init()
delay(1 * ms)
self.u0.init()
delay(1 * ms)
self.u0.set_frequency(1 * MHz)
self.u0.set_att_mu(255)
# disable ram
self.u0.set_cfr1(ram_enable=0)
self.u0.cpld.io_update.pulse_mu(8)
# config profile
self.u0.set_profile_ram(
start=0,
end=0 + len(data) - 1,
step=(1 << 16) - 1,
profile=0,
mode=ad9910.RAM_MODE_RAMPUP,
)
self.u0.cpld.set_profile(0)
self.u0.cpld.io_update.pulse_mu(8)
# write ram
delay(1 * ms)
self.u0.write_ram(data)
# turn on ttl
self.ttl5.on()
# enable ram playback
delay(1 * ms)
self.u0.set_cfr1(
ram_destination=ad9910.RAM_DEST_ASF, ram_enable=1, osk_enable=0
)
delay(1 * ms)
self.u0.cpld.io_update.pulse_mu(8)
self.u0.sw.on()
