I am not very familiar with computer, so I apologize for asking simple questions.
I am following the instruction on Urukul on page (10)[http://m-labs.science/docs/sinara-datasheets/4410-4412.pdf]
def prepare(self):
self.amp = [0.0, 0.0, 0.0, 0.7, 0.0, 0.7, 0.7] # Reversed Order
self.asf_ram = [0] * len(self.amp)
@kernel
def init_dds(self, dds):
self.core.break_realtime()
dds.init()
dds.set_att(6.*dB)
dds.cfg_sw(True)
@kernel
def configure_ram_mode(self, dds):
self.core.break_realtime()
dds.set_cfr1(ram_enable=0)
self.cpld.io_update.pulse_mu(8)
self.cpld.set_profile(0) # Enable the corresponding RAM profile
# Profile 0 is the default
dds.set_profile_ram(start=0, end=len(self.asf_ram)-1,
step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP)
self.cpld.io_update.pulse_mu(8)
dds.amplitude_to_ram(self.amp, self.asf_ram)
dds.write_ram(self.asf_ram)
self.core.break_realtime()
dds.set(frequency=5*MHz, ram_destination=RAM_DEST_ASF)
# Pass osk_enable=1 to set_cfr1() if it is not an amplitude RAM
dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)
self.cpld.io_update.pulse_mu(8)
@kernel
def run(self):
self.core.reset()
self.core.break_realtime()
self.cpld.init()
self.init_dds(self.dds0)
self.configure_ram_mode(self.dds0)
I have couple questions to understand this demonstration
- Previous examples, there was no use of RAM, what is the benefit for using RAM for modulating signals?
- What is cpld, and why are we initialized this (even if we are not using it directly)
- What is break_realtime, RAM_DESK_ASF, RAM_MODE_COUNT_RAMPUP, cfr?
- Where are we defining time sequence of pulses (i.e 2 microsecond pulse, 1 microsecond no signal)