- Edited
Hi, I'm trying to test RAM mode on AD9910, but find the following can work for Urukuls on the master crate but underflows for satellite crate.
Artiq 7.8173, installed on windows11 via conda
RAM works for urukul0, urukul1, urukul2 on master crate, underflows for urukul3 on satellite crate (independent simple test of frequency setting works well).
The code is as below:
`from artiq.experiment import *
from artiq.coredevice import ad9910
import numpy as np
total_time =30000
N = 500##ns
step_time=int(round(total_time/N))
class Test_dds(EnvExperiment):
"""ram-test"""
def build(self):
self.setattr_device("core")
self.setattr_device("urukul2_cpld") #Urukul module
self.setattr_device("urukul2_ch0") #Urukul module
self.u = self.urukul2_ch0
def prepare(self):
#create list of frequencies in FTW format to write to RAM
self.amp = [0.]*N
self.amp_ram = [0]*N
for i in range(len(self.amp)):
self.amp[i] = (i + 1) / len(self.amp)
self.u.amplitude_to_ram(self.amp,self.amp_ram)
print(self.amp,self.amp_ram)
@kernel
def run(self):
self.core.reset()
delay(5*ms)
self.u.cpld.init()
self.u.init()
delay(5000*us)
self.u.sw.off()
self.u.set_att(13.0*dB)
self.u.cpld.io_update.pulse(8*ns)
self.core.break_realtime()
'''prepare RAM profile:'''
self.u.set_cfr1(ram_enable=0) #disable RAM for writing data
delay(1000*us)#nice100#10
self.u.set_frequency(110.0*MHz)
self.u.cpld.io_update.pulse_mu(8) #I/O pulse to enact RAM change
self.u.set_profile_ram(start=0, end=N-1, step=step_time, profile=0, mode=ad9910.RAM_MODE_RAMPUP)
self.u.cpld.set_profile(0)
self.u.cpld.io_update.pulse_mu(8)
'''write data to RAM:'''
delay(1000*us)
self.u.write_ram(self.amp_ram)
delay(1000*us)
self.u.cpld.io_update.pulse_mu(10)
self.u.set_cfr1(ram_enable =1, ram_destination=ad9910.RAM_DEST_ASF, osk_enable=0)
self.u.sw.on()
self.u.cpld.io_update.pulse_mu(10)
delay(total_time*ns)
self.u.sw.off()`Bug reports:
root:Terminating with exception (RTIOUnderflow: RTIO underflow at 13499401172824 mu, channel 65552, slack -10048 mu)Core Device Traceback:
Traceback (most recent call first):
File "ksupport/rtio.rs", line 69, column 14, in (Rust function)
<unknown>
^
File "<artiq>\coredevice\spi2.py", line 225, in ... artiq.coredevice.spi2.SPIMaster.write<artiq.coredevice.spi2.SPIMaster>(...) (RA=+0xb38)
rtio_output((self.channel << 8) | SPI_DATA_ADDR, data)
File "<artiq>\coredevice\ad9910.py", line 346, in ... artiq.coredevice.ad9910.AD9910.write_ram<artiq.coredevice.ad9910.AD9910>(...) (inlined)
self.bus.write(data[i])
File "D:\OneDrive\artiq-exp-old\repository\0-atom\gauss ram-single origin.py", line 105, in artiq_worker_gauss ram-single origin.Test_dds.run(..., ...) (inlined)
self.u.write_ram(self.amp_ram)
artiq.coredevice.exceptions.RTIOUnderflow(0): RTIO underflow at 13499401172824 mu, channel 65552, slack -10048 mu
End of Core Device Traceback
Traceback (most recent call last):
File "C:\anaconda3\envs\artiq7\lib\site-packages\artiq\master\worker_impl.py", line 343, in main
exp_inst.run()
File "C:\anaconda3\envs\artiq7\lib\site-packages\artiq\language\core.py", line 54, in run_on_core
return getattr(self, arg).run(run_on_core, ((self,) + k_args), k_kwargs)
File "C:\anaconda3\envs\artiq7\lib\site-packages\artiq\coredevice\core.py", line 140, in run
self._run_compiled(kernel_library, embedding_map, symbolizer, demangler)
File "C:\anaconda3\envs\artiq7\lib\site-packages\artiq\coredevice\core.py", line 130, in _run_compiled
self.comm.serve(embedding_map, symbolizer, demangler)
File "C:\anaconda3\envs\artiq7\lib\site-packages\artiq\coredevice\comm_kernel.py", line 716, in serve
self._serve_exception(embedding_map, symbolizer, demangler)
File "C:\anaconda3\envs\artiq7\lib\site-packages\artiq\coredevice\comm_kernel.py", line 698, in _serve_exception
raise python_exn
artiq.coredevice.exceptions.RTIOUnderflow: RTIO underflow at 13499401172824 mu, channel 65552, slack -10048 mu
