I recently received a new set of crates (mitll7master and mitll7satellite) and am testing them out to make sure everything works. I am running into an issue where the urukuls an error "no valid window/delay" every time an init() call is attempted. I can leave out the init() call and the device is controlled fine, but I was accustomed to calling init() in at the beginning of every experiment.
Here is a minimal example of this which fails with the error:
from artiq.experiment import *
class DummyExperiment(EnvExperiment):
"""Dummy Experiment"""
def build(self):
self.setattr_device("core")
self.setattr_device("urukul3_ch0")
@kernel
def run(self):
self.core.reset()
self.core.break_realtime()
self.urukul2_ch0.init()
self.urukul2_ch0.set(1*MHz, 0.1)
self.urukul2_ch0.sw.on()
The same example with the init() call commented out works fine.
The error message:
root:Terminating with exception (ValueError: no valid window/delay)
Core Device Traceback:
Traceback (most recent call first):
File "<artiq>/coredevice/ad9910.py", line 1037, column 9, in ... artiq.coredevice.ad9910.AD9910.tune_sync_delay<artiq.coredevice.ad9910.AD9910>(...)
raise ValueError("no valid window/delay")
^
File "/tmp/tmpu2cv90kh/dummy.py", line 14, in artiq_worker_dummy.DummyExperiment.run(..., ...) (RA=+0x154)
self.urukul3_ch0.init()
File "<artiq>/coredevice/ad9910.py", line 510, in ... artiq.coredevice.ad9910.AD9910.init<artiq.coredevice.ad9910.AD9910>(...) (RA=+0xabc)
self.tune_sync_delay(self.sync_data.sync_delay_seed)
File "<artiq>/coredevice/ad9910.py", line 0, in ... artiq.coredevice.ad9910.AD9910.tune_sync_delay<artiq.coredevice.ad9910.AD9910>(...) (RA=+0x1100)
<unknown>
ValueError(0): no valid window/delay
End of Core Device Traceback
Traceback (most recent call last):
File "/nix/store/bv5y8vvhk0i0az68vrhkqcydmi2ch7rv-python3-3.9.16-env/lib/python3.9/site-packages/artiq/master/worker_impl.py", line 343, in main
exp_inst.run()
File "/nix/store/bv5y8vvhk0i0az68vrhkqcydmi2ch7rv-python3-3.9.16-env/lib/python3.9/site-packages/artiq/language/core.py", line 54, in run_on_core
return getattr(self, arg).run(run_on_core, ((self,) + k_args), k_kwargs)
File "/nix/store/bv5y8vvhk0i0az68vrhkqcydmi2ch7rv-python3-3.9.16-env/lib/python3.9/site-packages/artiq/coredevice/core.py", line 140, in run
self._run_compiled(kernel_library, embedding_map, symbolizer, demangler)
File "/nix/store/bv5y8vvhk0i0az68vrhkqcydmi2ch7rv-python3-3.9.16-env/lib/python3.9/site-packages/artiq/coredevice/core.py", line 130, in _run_compiled
self.comm.serve(embedding_map, symbolizer, demangler)
File "/nix/store/bv5y8vvhk0i0az68vrhkqcydmi2ch7rv-python3-3.9.16-env/lib/python3.9/site-packages/artiq/coredevice/comm_kernel.py", line 716, in serve
self._serve_exception(embedding_map, symbolizer, demangler)
File "/nix/store/bv5y8vvhk0i0az68vrhkqcydmi2ch7rv-python3-3.9.16-env/lib/python3.9/site-packages/artiq/coredevice/comm_kernel.py", line 698, in _serve_exception
raise python_exn
ValueError: no valid window/delay
Do I not need to init() call after all? Or am I losing out on timing performance with this failing? I have tested the phase stability of the urukul relative to a TTL pulse, and while it is roughly phase stable, there is slow phase drift of the urukul output relative to the TTL pulse at about 2pi per second wall clock time. See this sample experiment:
from artiq.experiment import *
class DummyExperiment(EnvExperiment):
"""Dummy Experiment"""
def build(self):
self.setattr_device("core")
self.setattr_device("urukul2_ch0")
self.setattr_device("ttl4")
def prepare(self):
self.freq_mu = self.urukul2_ch0.frequency_to_ftw(100*MHz)
self.amp_mu = self.urukul2_ch0.amplitude_to_asf(1)
self.phase_mu = self.urukul2_ch0.turns_to_pow(0)
@kernel
def run(self):
self.core.reset()
self.core.break_realtime()
# self.urukul3_ch0.init()
for _ in range(1000000):
t = self.core.get_rtio_counter_mu()
with parallel:
self.urukul2_ch0.set_mu(self.freq_mu, asf=self.amp_mu, pow_=self.phase_mu, ref_time_mu=t)
delay(10*us)
self.urukul2_ch0.sw.on()
self.ttl4.on()
delay(10*us)
self.urukul2_ch0.sw.off()
self.ttl4.off()
On my previous crate, a test like this was much more solid with no noticeable phase drift. I tried to upload my device_db.py file but am apparently not able to. It is the default device_db file for this system, though.