iCE40HX8K-EVB and sys_rst

kirill

Hi, I'm developing some design for iCE40HX8K-EVB board and stuck with sys_rst signal. If I try to use verlilog.convert, than resulting verilog file will contain sys_rst, and I can't map it anywhere, since arachne-pnr doesn't have any info in its chipdb. But if ice40_hx8k_b_evn.Platform().build is called than sys_rst is wired to int_rst register in resulting verilog file. So my questing is - how can I map sys_rst to int_rst on python side, to get same resulting verilog as platform.build()?

sb10q

You want to rename sys_rst to int_rst in the Verilog output?
Migen or nMigen?

kirill

Migen. No, it's seems that my board does not have a reset signal, in build procedure there is an emulation of rst signal. I wanted to understand how it's possible to get same verilog output in verilog.convert as in platform.build.

sb10q

Maybe what you are looking for is the ios parameter of verilog.convert?
Or generally, look at the source code to see how platform.build calls verilog.convert.