call to get_channel_att is erazing the existing attenuation values

mkc

I have a 8 channel SUServo setup using ARTIQ-7 I am trying to configure the PID loops individually by providing different attenuation values.

Following is the code snippet

 @kernel
     def init(self):
    channel_att = [0.,0.,0.,0.]
    self.core.break_realtime()
    self.core.reset()
    self.suservo0.init()
    delay(1*us)
    self.suservo0.set_pgia_mu(self.channelId, self.pgia_gain)
    delay(10*us)

    # DDS attenuator
     channel_att[0] = self.suservo0.cplds[0].get_channel_att(self.channelId)
     delay(10*ms)
     self.suservo0.cplds[0].set_att(self.channelId, self.attn)
    `

What I observe is, call to get_channel_att erases the attentuation set on all the channels. After the call to get_channel_att all the attentuation values are set to max 31.5 dBm.
Looking at the dcocumentation, I find SPI call sequence to read the register CS_ATT.

Is this a gateware bug or some other hardware issue.
Let me know if someone else hit a similar issue. I am attaching the coremgmt log for reference below.
[ 0.000016s] INFO(runtime): ARTIQ runtime starting... [ 0.003941s] INFO(runtime): software ident 7.8112.de6f444;nqcc-suservo [ 0.010568s] INFO(runtime): gateware ident 7.8112.de6f444;nqcc-suservo [ 0.017200s] INFO(runtime): log level set to INFO by default [ 0.022926s] INFO(runtime): UART log level set to INFO by default [ 0.139733s] WARN(runtime::rtio_clocking): rtio_clock setting not recognised. Falling back to default. [ 0.147836s] INFO(runtime::rtio_clocking): using internal 125MHz RTIO clock [ 0.424326s] INFO(board_artiq::si5324): waiting for Si5324 lock... [ 5.231496s] INFO(board_artiq::si5324): ...locked [ 5.236631s] INFO(runtime::rtio_clocking::crg): Using internal RTIO clock [ 5.267730s] INFO(runtime): network addresses: MAC=fc-0f-e7-07-68-06 IPv4=172.18.0.33 IPv6-LL=fe80::fe0f:e7ff:fe07:6806 IPv6=no configured address [ 5.281342s] INFO(board_artiq::drtio_routing): could not read routing table from configuration, using default [ 5.290058s] INFO(board_artiq::drtio_routing): routing table: RoutingTable { 0: 0; 1: 1 0; 2: 2 0; 3: 3 0; } [ 5.318002s] INFO(runtime::mgmt): management interface active

rjo

There is no read back in suservo. You can't currently read the attenuator values.

mkc

rjo
Thanks for a quick response. Could you please suggest the correct method for setting the attn? If I use
self.suservo0.cplds[0].set_att(self.channelId, self.attn)
without calling the get_channel_att, I still end up loosing the attenuation on other channels.
The logic behind calling get_channel_att was motivated from the fact that set_att code uses self.att_reg which should have been read in a previous call as the document suggests

@kernel
def set_att_mu(self, channel: TInt32, att: TInt32):
    """Set digital step attenuator in machine units.

    This method will also write the attenuator settings of the three
    other channels. **Use :meth:`get_att_mu` to retrieve the hardware**
    state set in previous experiments.

    :param channel: Attenuator channel (0-3).
    :param att: 8-bit digital attenuation setting:
        255 minimum attenuation, 0 maximum attenuation (31.5 dB)
    """
    a = self.att_reg & ~(0xff << (channel * 8))
    a |= att << (channel * 8)
    self.set_all_att_mu(a)`

mkc

If anyone encouters this issue, I would like them to know that without the support for read in SUServo, attenuation needs to be set simultaneously on all the four channels belonging to a cpld device.