Limits of sampling in parallel

barungz100

Hello,

My goal is to have the Zotino output a ramp while a Sampler is taking multiple samples in parallel.

System:
Artiq software/ gateware 8.0, Kasli v2.0, Zotino v1.3, Sampler v2.2

Please have a look at the following examples where there is only one sample taken:

(1)

@kernel
def run_kernel(self):
    self.core.reset()
    voltages = [...]
    loop_step_time = 50

    with parallel:

        for i in range(self.loop_range):
            self.zotino0.write_dac_mu(0, voltages[i])
            self.zotino0.load()
            delay(loop_steptime*us)

        with sequential:
            delay(loop_steptime*us)
            self.s0.sample_mu(smp)

(2)

@kernel
def run_kernel(self):
    self.core.reset()
    voltages = [...]
    loop_step_time = 50
    loop_step_time_mu = self.core.seconds_to_mu(loop_steptime)

    t0_cycle = now_mu()
    with parallel:

        for i in range(self.loop_range):
            at_mu(t0_cycle + i*loop_steptime_mu)
            self.zotino0.write_dac_mu(0, voltages[i])
            self.zotino0.load()

        with sequential:
            at_mu(t0_cycle + loop_steptime_mu)
            self.s0.sample_mu(smp)

What happens:
(1) will result in RTIOUnderflow if the self.loop_range is too large. Increasing the delay before taking a sample results in it seemingly getting stuck.
(2) also results in sequence error or getting stuck.

Questions:

Is sampling in parallel not possible? I understand that taking a sample is an instruction in the past, but are all other actions held up by the CPU before a sample is rendered?
I switched self.s0.sample_mu(smp) for self.ttl.off(), and the program indeed doesn't get stuck any longer. But sequence errors remain, with a limit around self.loop_range = 1000. Is this how deep one FIFO lane can go before overflowing another? Can I circumvent this by setting the second operation in parallel to another lane first?