I would like to test the new DRG function in ARTIQ_Beta and I met this problem when I call method to set DRGCTL and DRGHOLD:
NotImplementedError(0): This function is not implemented for this Urukul version.
I thought it was caused by the wrong CPLD version, which should be 0x09 but is now 0x08. How may I update my Urukul CPLD version to 0x09 ?

I can see that the CFG configuration register bit offsets definition has already changed in CPLD ProtoRev9. Is it means that if I would like to introduce new feature of Urukul to my codes, I need to generate new gateware and reflash the ARTIQ?

You need to reflash the Urukul CPLD. Binaries are on Hydra.