Hi,

I am looking to use the PhasedAccu from duc.py in MiSoC.

https://github.com/m-labs/misoc/blob/master/misoc/cores/duc.py#L233

My application requires 12 phases which is not a power of two as imposed by log2_int here
https://github.com/m-labs/misoc/blob/master/misoc/cores/duc.py#L257

and also exceeds the current capabilities of the MCM module as seen here:
https://github.com/m-labs/misoc/blob/master/misoc/cores/duc.py#L196

When expanding MCM to go up to 16 constants I started running into timing closure issues on Artix7 fabric. I think 12 might actually be doable. Allowing for one extra cycle of latency in MCM seems to allow for up to 16 constant - but it obviously breaks the test case for duc.py.

Regardless of how one resolved the MCM issue, using a non-power-of-two number of phases results in an Exception thrown and simply letting need_pow2=False here
https://github.com/m-labs/migen/blob/master/migen/fhdl/bitcontainer.py#L7
results in output consistent with the nearest higher power of two phases, i.e.
0x10, 0x20, 0x30, 0x40 0x50,... would be expected for f=(0x10 << 16) and three phases
0x10, 0x20,0x30,0x50,0x60,... is obtained (this looks like the 4th phase is missing)
See this test case for reference:
https://github.com/m-labs/misoc/blame/master/misoc/test/test_duc.py#L41

So now my question is what is the best way to allow PhasedAccu to run with 12 phases? My frequency target is 200 MHz on Artix7 fabric. Guidance on the approach for this will be much appreciated!

Thanks!
Felix

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