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All Discussions
DRTIO with zc706 master and kasli v1.1 satellite
strange behavior when using gate_rising() function
How to fit the data in ARTIQ during experimental run?
Simultaneous control of more than one channel of Zotino
RTIO event submission if lane FIFO is full
Error while building the Kasli gateware image
OSError: source code not available
Ignored delays and infinite wait after installing satellite
Parallel control Fastino channels
Issues with running DDS channels from AD9910 and Ad9912
Does MiSoC Support RT-Linux?
Start immediately after rising edge detected
Vivado problem during firmware build
RTIO clock frequency for Kasli (cu3)
Proper Alias Format?
ARTIQ Reset
Error when updating dual_iir settings
How do AD9914 moninj probes work?
Serial connection between host and Kasli
Target for Kasli_SoC does not exist
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