Line Trigger

GuanQun

Hello, when I use a 50hz square wave to trigger another pulse sequence,why is its period changing?20ms、10ms，the code is as following，build part is omitted ，I am puzzled：
`

@kernel #this code runs on the FPGA
def run(self):
	self.core.reset()                       #resets core device
	self.ttl0.input()
	self.ttl30.output()                       #sets TTL0 as an input
	self.ttl6.output()                       #sets TTL0 as an input                   #sets TTL6 as an output
	delay(1*us) 
	for i in range(1000000):                            #1us delay, necessary for using trigger, no error given if removed
		gate_end_mu=self.ttl0.gate_rising(20*ms)    #opens gate for rising edges to be detected on TTL0 for 10ms
												#sets variable t_end as time(in MUs) at which detection stops                                        
		t_edge=self.ttl0.timestamp_mu(gate_end_mu)  #sets variable t_edge as time(in MUs) at which first edge is detected
												#if no edge is detected, sets t_edge to -1
		if t_edge>0:
			at_mu(t_edge)
			delay(500*us)                       #set time cursor to position of edge
			self.ttl30.on()
			delay(3*ms)
			self.ttl30.off()
            
			self.core.reset()`

Kaifeng

You can refer to this:
https://forum.m-labs.hk/d/108-triggered-experiment-start-with-subsequent-ttl-input/2

isaac

I'd like to provide a more efficient way that reduces the waiting time after the rising edges coming.

@kernel
def sync(self, delay_time):
        self.core.wait_until_mu(now_mu())
        t_edge = -1
        while t_edge<0:
            at_mu(rtio_get_counter() + delay_time) # rtio_get_counter() imported from artiq.coredevice.core
            gate_end_mu = self._sync_ch.gate_rising(1*ms) # TTLInOut
            t_edge = self._sync_ch.timestamp_mu(gate_end_mu)
            delay(1*us)
            self.core.wait_until_mu(now_mu())
        at_mu(t_edge)
        delay(1*ms)

We use the code to synchronize magnetic noise critical procedures with the 50 Hz AC.

niwotongzai

isaac

niwotongzai

isaac Hi, could you help me with synchronize rising edges using this code? I fond it will underflow when use this code to sync inside a for loop. It can be solved by using core.reset(), but core.reset will cause other code not run well.

dpn

Here's a slightly more robust version (handles missing triggers, old left-over events):

@kernel
def wait_for_trigger(self):
    gate_open_mu = now_mu()
    self.trigger._set_sensitivity(1)

    # Loop until any old left-over events (before current gate open) are
    # consumed, or the specified timeout has elapsed.
    t_trig_mu = 0
    while True:
        t_trig_mu = self.trigger.timestamp_mu(gate_open_mu + self.max_wait_mu)
        if t_trig_mu < 0 or t_trig_mu >= gate_open_mu:
            break

    at_mu(self.core.get_rtio_counter_mu() + self.slack_mu)
    self.trigger._set_sensitivity(0)

    if t_trig_mu < 0:
        raise MissingTrigger
    return t_trig_mu

We really should expose/document the raw edge sensitivity interface from the ttl drivers.

rjo

You want to drain the input fifo after closing the gate. Might not be critical for line trigger assuming you guarantee no bounces but it's the proper thing to do.

rjo

Here's another good implementation:
https://gitlab.com/atomiq-project/atomiq/-/commit/d523e88385724170bb68ae33db9664987663e728

I would still recommend handling overflows while draining before the gate and also draining after the gate.