The manual states that "The number of lanes is a hard limit on the number of simultaneous RTIO output events." and "By default, the SED has 8 lanes..."
How do I increase the number of lanes? Is there a downside? Why was a number of 8 lanes chosen?
Philipp How do I increase the number of lanes?
They are defined at bitstream compilation time. Do you have an active firmware subscription with M-Labs?
Is there a downside?
Increasing the number of lanes increases FPGA resource usage and also makes timing closure more difficult.
I do not have an active subscription with M-Labs