FIFO lanes

Philipp

Hey,

The manual states that "The number of lanes is a hard limit on the number of simultaneous RTIO output events." and "By default, the SED has 8 lanes..."

How do I increase the number of lanes? Is there a downside? Why was a number of 8 lanes chosen?

sb10q

Philipp How do I increase the number of lanes?

They are defined at bitstream compilation time. Do you have an active firmware subscription with M-Labs?

Is there a downside?

Increasing the number of lanes increases FPGA resource usage and also makes timing closure more difficult.

han94ros

sb10q Hi Seb
I have an active firmware subscription with M-labs, how do I go about increasing the number of SED lanes.

Philipp

I do not have an active subscription with M-Labs

sb10q

Please email helpdesk at m-labs.hk and mention which variant you have.

sb10q

Though it seems that you won't need it: https://forum.m-labs.hk/d/227-help-request-with-scheduling-stages/18