Help request with scheduling stages

sb10q

han94ros finally I am getting these errors when running the scheduler with core.reset

Those aren't errors and things look normal.

han94ros

sb10q ok thanks for the confirmation.

lriesebos

Running separate kernels in a single experiment works fine if that is preferred (e.g. with seamless handover). Though as mentioned before, the time of compilation should not be neglected and personally I would merge it in one kernel just for that reason. I do not know how your preparation stage looks like, but I expect that the single-kernel approach is anyway going to be faster (wall-clock time) for such a "small" experiment. Regarding preparation, easiest is probably to just prepare all your data before you enter the single kernel. The Python language allows you to program that in many different convenient ways!

han94ros

lriesebos Ok that is what I had in mind to do so thanks for the confirmation. Thank you for all the advice on this scheduling issues, I really appreciate all your help.

han94ros

lriesebos

Hey Leon, I have implemented everything in a single kernel however I have not been able to overcome the RTIO underflow errors. I would really appreciate it if you could have a quick look over it and point out issue that may cause these errors.

The first section involves setting the attentuation and frequency of the AD9912 channels.

The second section relates to the ad9910 channels either setting single tone frequencies or performing frequency modulation using the RAM

The third section relates to the TTL output channels.

The fourth section involves setting the single tone analog outputs using the zotino

The fifth section which begins at self.list_of_amplitude_modulation_selector will allow for concurrent amplitude ramps of both the AD9910 and zotino channels.

The final section is the sampler collecting values from the 8 sampling channels.
`

 @kernel
def run(self):
self.core.reset()
delay(1 * s)
for p in range(self.number_of_scan_points):
    
    for h in range(self.number_of_repetitions):
        
        for i in self.list_of_active_stages:
            
       
            
            
            
            t0 = now_mu()

    
            self.DDS_ad9912_channel0.set_att(self.list_ad9912_channel0_atten[i])
            self.DDS_ad9912_channel1.set_att(self.list_ad9912_channel1_atten[i])
            self.DDS_ad9912_channel2.set_att(self.list_ad9912_channel2_atten[i])
            self.DDS_ad9912_channel3.set_att(self.list_ad9912_channel3_atten[i])
    
  
    
            self.DDS_ad9912_channel0.set(self.list_ad9912_channel0_freq[i] * MHz)
            self.DDS_ad9912_channel1.set(self.list_ad9912_channel1_freq[i] * MHz)
            self.DDS_ad9912_channel2.set(self.list_ad9912_channel2_freq[i] * MHz)
            self.DDS_ad9912_channel3.set(self.list_ad9912_channel3_freq[i] * MHz)
    
            if self.list_parameter_ch3[i] == 0:
                self.DDS_ad9910_channel3.set_cfr1(ram_enable=0)
                self.DDS_ad9910_channel3.cpld.io_update.pulse(100*ns)
                self.DDS_ad9910_channel3.set_att(self.list_ad9910_channel3_atten[i])
                self.DDS_ad9910_channel3.set(self.list_ad9910_channel3_freq[i] * MHz, amplitude = self.list_ad9910_channel3_amp[i])
    
            if self.list_parameter_ch3[i] == 1:
                '''Urukul0 - Channel 3'''
                '''initialize DDS channel'''
                self.DDS_ad9910_channel3.cpld.io_update.pulse(100*ns)
                self.DDS_ad9910_channel3.set_amplitude(1.)
                self.DDS_ad9910_channel3.set_att(0.*dB)
                self.DDS_ad9910_channel3.set(100.*MHz)
 
                '''prepare RAM profile:'''
                self.DDS_ad9910_channel3.set_cfr1(ram_enable=0) #disable RAM for writing data
                self.DDS_ad9910_channel3.cpld.io_update.pulse(100*ns) #I/O pulse to enact RAM change
                self.DDS_ad9910_channel3.set_profile_ram(start=0, end=self.N-1, step=self.list_t_step_3[i], profile=0, mode=ad9910.RAM_MODE_CONT_RAMPUP)
                self.DDS_ad9910_channel3.cpld.set_profile(0)
                self.DDS_ad9910_channel3.cpld.io_update.pulse(100*ns)
 
                '''write data to RAM:'''
                self.DDS_ad9910_channel3.write_ram(self.list_f_ram_3[i])
                
                '''enable RAM mode (enacted by IO pulse) and fix other parameters:'''
                self.DDS_ad9910_channel3.set_cfr1(internal_profile=0, ram_enable = 1, ram_destination=ad9910.RAM_DEST_FTW, manual_osk_external=0, osk_enable=1, select_auto_osk=0)
                self.DDS_ad9910_channel3.sw.on()
                self.DDS_ad9910_channel3.cpld.io_update.pulse_mu(8)
    
            if self.list_parameter_ch2[i] == 0:
                self.DDS_ad9910_channel2.set_cfr1(ram_enable=0)
                self.DDS_ad9910_channel2.cpld.io_update.pulse(100*ns)
                self.DDS_ad9910_channel2.set_att(self.list_ad9910_channel2_atten[i])
                self.DDS_ad9910_channel2.set(self.list_ad9910_channel2_freq[i] * MHz, amplitude = self.list_ad9910_channel2_amp[i])
    

            if self.list_parameter_ch2[i] == 1:
                '''Urukul0 - Channel 2'''

                '''initialize DDS channel'''
                self.DDS_ad9910_channel2.cpld.io_update.pulse(100*ns)
                self.DDS_ad9910_channel2.set_amplitude(1.)
                self.DDS_ad9910_channel2.set_att(0.*dB)
                self.DDS_ad9910_channel2.set(100.*MHz)
 
                '''prepare RAM profile:'''
                self.DDS_ad9910_channel2.set_cfr1(ram_enable=0) #disable RAM for writing data
                self.DDS_ad9910_channel2.cpld.io_update.pulse(100*ns) #I/O pulse to enact RAM change
                self.DDS_ad9910_channel2.set_profile_ram(start=0, end=self.N-1, step=self.list_t_step_2[i], profile=0, mode=ad9910.RAM_MODE_CONT_RAMPUP)
                self.DDS_ad9910_channel2.cpld.set_profile(0)
                self.DDS_ad9910_channel2.cpld.io_update.pulse(100*ns)

 
                '''write data to RAM:'''
                self.DDS_ad9910_channel2.write_ram(self.list_f_ram_2[i])
 
 
                '''enable RAM mode (enacted by IO pulse) and fix other parameters:'''
                self.DDS_ad9910_channel2.set_cfr1(internal_profile=0, ram_enable = 1, ram_destination=ad9910.RAM_DEST_FTW, manual_osk_external=0, osk_enable=1, select_auto_osk=0)
                self.DDS_ad9910_channel2.sw.on()
                self.DDS_ad9910_channel2.cpld.io_update.pulse_mu(8)


            if self.list_parameter_ch1[i] == 0:
                self.DDS_ad9910_channel1.set_cfr1(ram_enable=0)
                self.DDS_ad9910_channel1.cpld.io_update.pulse(100*ns)
                self.DDS_ad9910_channel1.set_att(self.list_ad9910_channel1_atten[i])
                self.DDS_ad9910_channel1.set(self.list_ad9910_channel1_freq[i] * MHz, amplitude = self.list_ad9910_channel1_amp[i])

    
            if self.list_parameter_ch1[i] == 1:
                '''Urukul0 - Channel 1'''
                '''initialize DDS channel'''
                self.DDS_ad9910_channel1.cpld.io_update.pulse(100*ns)
                self.DDS_ad9910_channel1.set_amplitude(1.)
                self.DDS_ad9910_channel1.set_att(0.*dB)
                self.DDS_ad9910_channel1.set(100.*MHz)
 
                '''prepare RAM profile:'''
                self.DDS_ad9910_channel1.set_cfr1(ram_enable=0) #disable RAM for writing data
                self.DDS_ad9910_channel1.cpld.io_update.pulse(100*ns) #I/O pulse to enact RAM change
                self.DDS_ad9910_channel1.set_profile_ram(start=0, end=self.N-1, step=self.list_t_step_1[i], profile=0, mode=ad9910.RAM_MODE_CONT_RAMPUP)
                self.DDS_ad9910_channel1.cpld.set_profile(0)
                self.DDS_ad9910_channel1.cpld.io_update.pulse(100*ns)

 
                '''write data to RAM:'''
                self.DDS_ad9910_channel1.write_ram(self.list_f_ram_1[i])

 
                '''enable RAM mode (enacted by IO pulse) and fix other parameters:'''
                self.DDS_ad9910_channel1.set_cfr1(internal_profile=0, ram_enable = 1, ram_destination=ad9910.RAM_DEST_FTW, manual_osk_external=0, osk_enable=1, select_auto_osk=0)
                self.DDS_ad9910_channel1.sw.on()
                self.DDS_ad9910_channel1.cpld.io_update.pulse_mu(8)
    
            if self.list_parameter_ch0[i] == 0:
                self.DDS_ad9910_channel0.set_cfr1(ram_enable=0)
                self.DDS_ad9910_channel0.cpld.io_update.pulse(100*ns)
                self.DDS_ad9910_channel0.set_att(self.list_ad9910_channel0_atten[i])
                self.DDS_ad9910_channel0.set(self.list_ad9910_channel0_freq[i] * MHz, amplitude = self.list_ad9910_channel0_amp[i])

            if self.list_parameter_ch0[i] == 1:
                '''Urukul0 - Channel 1'''
                '''initialize DDS channel'''
                self.DDS_ad9910_channel0.cpld.io_update.pulse(100*ns)
                self.DDS_ad9910_channel0.set_amplitude(1.)
                self.DDS_ad9910_channel0.set_att(0.*dB)
                self.DDS_ad9910_channel0.set(100.*MHz)
 
                '''prepare RAM profile:'''
                self.DDS_ad9910_channel0.set_cfr1(ram_enable=0) #disable RAM for writing data
                self.DDS_ad9910_channel0.cpld.io_update.pulse(100*ns) #I/O pulse to enact RAM change
                self.DDS_ad9910_channel0.set_profile_ram(start=0, end=self.N-1, step=self.list_t_step_0[i], profile=0, mode=ad9910.RAM_MODE_CONT_RAMPUP)
                self.DDS_ad9910_channel0.cpld.set_profile(0)
                self.DDS_ad9910_channel0.cpld.io_update.pulse(100*ns)

 
                '''write data to RAM:'''
                self.DDS_ad9910_channel0.write_ram(self.list_f_ram_0[i])
                
                
                '''enable RAM mode (enacted by IO pulse) and fix other parameters:'''
                self.DDS_ad9910_channel0.set_cfr1(internal_profile=0, ram_enable = 1, ram_destination=ad9910.RAM_DEST_FTW, manual_osk_external=0, osk_enable=1, select_auto_osk=0)
                self.DDS_ad9910_channel0.sw.on()
                self.DDS_ad9910_channel0.cpld.io_update.pulse_mu(8)


            if self.list_ttl4[i] == "on":
                self.ttl_channel4.on()
            else:
                self.ttl_channel4.off()
                
            delay (100 * ns)
    
            if self.list_ttl5[i] == "on":
                self.ttl_channel5.on()
            else:
                self.ttl_channel5.off()            
                
            delay (100 * ns)
            
            
            if self.list_ttl6[i] == "on":
                self.ttl_channel6.on()
            else:
                self.ttl_channel6.off()
            
            delay (100 * ns)
            
            if self.list_ttl7[i] == "on":
                self.ttl_channel7.on()
            else:
                self.ttl_channel7.off()
            
            delay (100 * ns)
            
            if self.list_ttl8[i] == "on":
                self.ttl_channel8.on()
            else:
                self.ttl_channel8.off()
  
            delay (100 * ns)
            
            if self.list_ttl9[i] == "on":
                self.ttl_channel9.on()
            else:
                self.ttl_channel9.off()
        
            delay (100 * ns)
            
            if self.list_ttl10[i] == "on":
                self.ttl_channel10.on()
            else:
                self.ttl_channel10.off()
                
                
            delay (100 * ns)
            
            
            if self.list_ttl11[i] == "on":
                self.ttl_channel11.on()
            else:
                self.ttl_channel11.off()
    
    
    
            delay (100 * ns)
            
            
            if self.list_ttl12[i] == "on":
                self.ttl_channel12.on()
            else:
                self.ttl_channel12.off()
    
    
            delay (100 * ns)
            
            
            if self.list_ttl13[i] == "on":
                self.ttl_channel13.on()
            else:
                self.ttl_channel13.off()
    
    
            delay (100 * ns)
            
            if self.list_ttl14[i] == "on":
                self.ttl_channel14.on()
            else:
                self.ttl_channel14.off()
    
            delay (100 * ns)
            
            if self.list_ttl15[i] == "on":
                self.ttl_channel15.on()
            else:
                self.ttl_channel15.off()
    
 
            
            if self.list_of_zotino_ramp_selector[i] == 1:
                for u in range(len(self.list_of_updated_voltages)):
                    self.zotino0.write_dac(self.list_of_dac_channels[i][u], self.list_of_updated_voltages[i][u])
                    self.zotino0.load()
                    # delay(1 * us)
                    

            else:
                for u in range(len(self.list_voltages)):
                    self.zotino0.write_dac(self.list_of_dac_channels[i][u], self.list_voltages[i][u])
                    self.zotino0.load()
                    # delay(1 * us)
                    
      
            if self.list_of_amplitude_modulation_selector[i] == 1:
                
                if self.list_parameter_ch0[i] == 2:
                    self.DDS_ad9910_channel0.set_cfr1(ram_enable=0)
                    self.DDS_ad9910_channel0.cpld.io_update.pulse(100*ns)
                    self.DDS_ad9910_channel0.set_att(self.list_ad9910_channel0_atten[i])
                    delay(1 * us)
                    self.DDS_ad9910_channel0.set(self.list_ad9910_channel0_freq[i] * MHz, amplitude = 1.0)

                if self.list_parameter_ch1[i] == 2:
                    self.DDS_ad9910_channel1.set_cfr1(ram_enable=0)
                    self.DDS_ad9910_channel1.cpld.io_update.pulse(100*ns)
                    self.DDS_ad9910_channel1.set_att(self.list_ad9910_channel1_atten[i])
                    delay(1 * us)
                    self.DDS_ad9910_channel1.set(self.list_ad9910_channel1_freq[i] * MHz, amplitude = 1.0)
                
                if self.list_parameter_ch2[i] == 2:
                    self.DDS_ad9910_channel2.set_cfr1(ram_enable=0)
                    self.DDS_ad9910_channel2.cpld.io_update.pulse(100*ns)
                    self.DDS_ad9910_channel2.set_att(self.list_ad9910_channel2_atten[i])
                    delay(1 * us)
                    self.DDS_ad9910_channel2.set(self.list_ad9910_channel2_freq[i] * MHz, amplitude = 1.0)
                
                if self.list_parameter_ch3[i] == 2:
                    self.DDS_ad9910_channel3.set_cfr1(ram_enable=0)
                    self.DDS_ad9910_channel3.cpld.io_update.pulse(100*ns)
                    self.DDS_ad9910_channel3.set_att(self.list_ad9910_channel3_atten[i])
                    delay(1 * us)
                    self.DDS_ad9910_channel3.set(self.list_ad9910_channel3_freq[i] * MHz, amplitude = 1.0)


                kk4 = 0
                for entry15 in self.final_time_list[i]:
                    if self.final_channel_list[i][kk4] == 3.01:
                        self.DDS_ad9910_channel3.set(self.list_ad9910_channel3_freq[i] * MHz, amplitude = self.final_voltage_list[i][kk4])
                    if self.final_channel_list[i][kk4] == 2.01:
                        self.DDS_ad9910_channel2.set(self.list_ad9910_channel2_freq[i] * MHz, amplitude = self.final_voltage_list[i][kk4])
                    if self.final_channel_list[i][kk4] == 1.01:
                        self.DDS_ad9910_channel1.set(self.list_ad9910_channel1_freq[i] * MHz, amplitude = self.final_voltage_list[i][kk4])
                    if self.final_channel_list[i][kk4] == 0.01:
                        self.DDS_ad9910_channel0.set(self.list_ad9910_channel0_freq[i] * MHz, amplitude = self.final_voltage_list[i][kk4])
                    if self.final_channel_list[i][kk4] == 0.0:
                        self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                        self.zotino0.load()
                    if self.final_channel_list[i][kk4] == 1.0:
                        self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                        self.zotino0.load()
                    if self.final_channel_list[i][kk4] == 2.0:
                        self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                        self.zotino0.load()
                    if self.final_channel_list[i][kk4] == 3.0:
                        self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                        self.zotino0.load()
                    if self.final_channel_list[i][kk4] == 4.0:
                        self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                        self.zotino0.load()
                    if self.final_channel_list[i][kk4] == 5.0:
                        self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                        self.zotino0.load()
                    if self.final_channel_list[i][kk4] == 6.0:
                        self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                        self.zotino0.load()
                    if self.final_channel_list[i][kk4] == 7.0:
                        self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                        self.zotino0.load()
                    if self.final_channel_list[i][kk4] == 8.0:
                        self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                        self.zotino0.load()
                    if self.final_channel_list[i][kk4] == 9.0:
                        self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                        self.zotino0.load()
                    if self.final_channel_list[i][kk4] == 10.0:
                        self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                        self.zotino0.load()
                    if self.final_channel_list[i][kk4] == 11.0:
                        self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                        self.zotino0.load()
                        
                    # print(now_mu()-t00, "execuetion time")
                    delay(self.final_time_list[i][kk4] * ns)
                    kk4 = kk4 + 1
                    
                    

            self.sampler0.sample(self.list_of_sampler_values[i])



            delay((self.list_t_duration[i] * ns) - (now_mu()-t0)*ns)`

connorgoham

This is just going to reiterate a point already made by Iriesebos, but I definitely recommend using as few separate kernel calls as possible. I find the compilation time of multiple kernel calls in a single experiment to be intolerable for day to day operations/experiments.

My general experimental format is to implement the run() method on the master that handles pauses and terminations, or otherwise calls a krun() method that then runs on the kernel. This krun() method executes all of the code that should run on the core device, and only exits & returns to the master once all of the kernel code is done, or if scheduler.check_pause() indicates it should exit early. Data collected during krun() is passed back to the master and analyzed on the fly using a combination of datasets and asynchronous RPC calls (e.g. for live plotting).

My interest in having an experiment auto schedule another is in the event an experiment detects ion loss, it pauses itself and schedules a recovery experiment. Upon termination of the recovery experiment, the original experiment then continues. My use of auto-scheduling is thus infrequent; not a standard part of my experimental sequence.

han94ros

connorgoham Thanks for the information Connor. I have placed all the contents to be run on the kernel in a single kernel as suggested however I am still getting RTIO underflow errors. I have read that you have spent a bit of time on ARTIQ, would you be kind enough to have a quick skim over the code and see how I can prevent these RTIO underflow errors.

@kernel
def run(self):
    self.core.reset()
    delay(1 * s)
    
    
    
    for p in range(self.number_of_scan_points):
        
        for h in range(self.number_of_repetitions):
            
            for i in self.list_of_active_stages:
                
           
                
                
                
                t0 = now_mu()

        
                self.DDS_ad9912_channel0.set_att(self.list_ad9912_channel0_atten[i])
                self.DDS_ad9912_channel1.set_att(self.list_ad9912_channel1_atten[i])
                self.DDS_ad9912_channel2.set_att(self.list_ad9912_channel2_atten[i])
                self.DDS_ad9912_channel3.set_att(self.list_ad9912_channel3_atten[i])
        
  
        
                self.DDS_ad9912_channel0.set(self.list_ad9912_channel0_freq[i] * MHz)
                self.DDS_ad9912_channel1.set(self.list_ad9912_channel1_freq[i] * MHz)
                self.DDS_ad9912_channel2.set(self.list_ad9912_channel2_freq[i] * MHz)
                self.DDS_ad9912_channel3.set(self.list_ad9912_channel3_freq[i] * MHz)
        
                if self.list_parameter_ch3[i] == 0:
                    self.DDS_ad9910_channel3.set_cfr1(ram_enable=0)
                    self.DDS_ad9910_channel3.cpld.io_update.pulse(100*ns)
                    self.DDS_ad9910_channel3.set_att(self.list_ad9910_channel3_atten[i])
                    self.DDS_ad9910_channel3.set(self.list_ad9910_channel3_freq[i] * MHz, amplitude = self.list_ad9910_channel3_amp[i])
        
                if self.list_parameter_ch3[i] == 1:
                    '''Urukul0 - Channel 3'''
                    '''initialize DDS channel'''
                    self.DDS_ad9910_channel3.cpld.io_update.pulse(100*ns)
                    self.DDS_ad9910_channel3.set_amplitude(1.)
                    self.DDS_ad9910_channel3.set_att(0.*dB)
                    self.DDS_ad9910_channel3.set(100.*MHz)
 
                    '''prepare RAM profile:'''
                    self.DDS_ad9910_channel3.set_cfr1(ram_enable=0) #disable RAM for writing data
                    self.DDS_ad9910_channel3.cpld.io_update.pulse(100*ns) #I/O pulse to enact RAM change
                    self.DDS_ad9910_channel3.set_profile_ram(start=0, end=self.N-1, step=self.list_t_step_3[i], profile=0, mode=ad9910.RAM_MODE_CONT_RAMPUP)
                    self.DDS_ad9910_channel3.cpld.set_profile(0)
                    self.DDS_ad9910_channel3.cpld.io_update.pulse(100*ns)
 
                    '''write data to RAM:'''
                    self.DDS_ad9910_channel3.write_ram(self.list_f_ram_3[i])
                    
                    '''enable RAM mode (enacted by IO pulse) and fix other parameters:'''
                    self.DDS_ad9910_channel3.set_cfr1(internal_profile=0, ram_enable = 1, ram_destination=ad9910.RAM_DEST_FTW, manual_osk_external=0, osk_enable=1, select_auto_osk=0)
                    self.DDS_ad9910_channel3.sw.on()
                    self.DDS_ad9910_channel3.cpld.io_update.pulse_mu(8)
        
                if self.list_parameter_ch2[i] == 0:
                    self.DDS_ad9910_channel2.set_cfr1(ram_enable=0)
                    self.DDS_ad9910_channel2.cpld.io_update.pulse(100*ns)
                    self.DDS_ad9910_channel2.set_att(self.list_ad9910_channel2_atten[i])
                    self.DDS_ad9910_channel2.set(self.list_ad9910_channel2_freq[i] * MHz, amplitude = self.list_ad9910_channel2_amp[i])
        
    
                if self.list_parameter_ch2[i] == 1:
                    '''Urukul0 - Channel 2'''

                    '''initialize DDS channel'''
                    self.DDS_ad9910_channel2.cpld.io_update.pulse(100*ns)
                    self.DDS_ad9910_channel2.set_amplitude(1.)
                    self.DDS_ad9910_channel2.set_att(0.*dB)
                    self.DDS_ad9910_channel2.set(100.*MHz)
 
                    '''prepare RAM profile:'''
                    self.DDS_ad9910_channel2.set_cfr1(ram_enable=0) #disable RAM for writing data
                    self.DDS_ad9910_channel2.cpld.io_update.pulse(100*ns) #I/O pulse to enact RAM change
                    self.DDS_ad9910_channel2.set_profile_ram(start=0, end=self.N-1, step=self.list_t_step_2[i], profile=0, mode=ad9910.RAM_MODE_CONT_RAMPUP)
                    self.DDS_ad9910_channel2.cpld.set_profile(0)
                    self.DDS_ad9910_channel2.cpld.io_update.pulse(100*ns)

 
                    '''write data to RAM:'''
                    self.DDS_ad9910_channel2.write_ram(self.list_f_ram_2[i])
 
 
                    '''enable RAM mode (enacted by IO pulse) and fix other parameters:'''
                    self.DDS_ad9910_channel2.set_cfr1(internal_profile=0, ram_enable = 1, ram_destination=ad9910.RAM_DEST_FTW, manual_osk_external=0, osk_enable=1, select_auto_osk=0)
                    self.DDS_ad9910_channel2.sw.on()
                    self.DDS_ad9910_channel2.cpld.io_update.pulse_mu(8)
    
    
                if self.list_parameter_ch1[i] == 0:
                    self.DDS_ad9910_channel1.set_cfr1(ram_enable=0)
                    self.DDS_ad9910_channel1.cpld.io_update.pulse(100*ns)
                    self.DDS_ad9910_channel1.set_att(self.list_ad9910_channel1_atten[i])
                    self.DDS_ad9910_channel1.set(self.list_ad9910_channel1_freq[i] * MHz, amplitude = self.list_ad9910_channel1_amp[i])

        
                if self.list_parameter_ch1[i] == 1:
                    '''Urukul0 - Channel 1'''
                    '''initialize DDS channel'''
                    self.DDS_ad9910_channel1.cpld.io_update.pulse(100*ns)
                    self.DDS_ad9910_channel1.set_amplitude(1.)
                    self.DDS_ad9910_channel1.set_att(0.*dB)
                    self.DDS_ad9910_channel1.set(100.*MHz)
 
                    '''prepare RAM profile:'''
                    self.DDS_ad9910_channel1.set_cfr1(ram_enable=0) #disable RAM for writing data
                    self.DDS_ad9910_channel1.cpld.io_update.pulse(100*ns) #I/O pulse to enact RAM change
                    self.DDS_ad9910_channel1.set_profile_ram(start=0, end=self.N-1, step=self.list_t_step_1[i], profile=0, mode=ad9910.RAM_MODE_CONT_RAMPUP)
                    self.DDS_ad9910_channel1.cpld.set_profile(0)
                    self.DDS_ad9910_channel1.cpld.io_update.pulse(100*ns)
    
 
                    '''write data to RAM:'''
                    self.DDS_ad9910_channel1.write_ram(self.list_f_ram_1[i])

 
                    '''enable RAM mode (enacted by IO pulse) and fix other parameters:'''
                    self.DDS_ad9910_channel1.set_cfr1(internal_profile=0, ram_enable = 1, ram_destination=ad9910.RAM_DEST_FTW, manual_osk_external=0, osk_enable=1, select_auto_osk=0)
                    self.DDS_ad9910_channel1.sw.on()
                    self.DDS_ad9910_channel1.cpld.io_update.pulse_mu(8)
        
                if self.list_parameter_ch0[i] == 0:
                    self.DDS_ad9910_channel0.set_cfr1(ram_enable=0)
                    self.DDS_ad9910_channel0.cpld.io_update.pulse(100*ns)
                    self.DDS_ad9910_channel0.set_att(self.list_ad9910_channel0_atten[i])
                    self.DDS_ad9910_channel0.set(self.list_ad9910_channel0_freq[i] * MHz, amplitude = self.list_ad9910_channel0_amp[i])

                if self.list_parameter_ch0[i] == 1:
                    '''Urukul0 - Channel 1'''
                    '''initialize DDS channel'''
                    self.DDS_ad9910_channel0.cpld.io_update.pulse(100*ns)
                    self.DDS_ad9910_channel0.set_amplitude(1.)
                    self.DDS_ad9910_channel0.set_att(0.*dB)
                    self.DDS_ad9910_channel0.set(100.*MHz)
 
                    '''prepare RAM profile:'''
                    self.DDS_ad9910_channel0.set_cfr1(ram_enable=0) #disable RAM for writing data
                    self.DDS_ad9910_channel0.cpld.io_update.pulse(100*ns) #I/O pulse to enact RAM change
                    self.DDS_ad9910_channel0.set_profile_ram(start=0, end=self.N-1, step=self.list_t_step_0[i], profile=0, mode=ad9910.RAM_MODE_CONT_RAMPUP)
                    self.DDS_ad9910_channel0.cpld.set_profile(0)
                    self.DDS_ad9910_channel0.cpld.io_update.pulse(100*ns)

 
                    '''write data to RAM:'''
                    self.DDS_ad9910_channel0.write_ram(self.list_f_ram_0[i])
                    
                    
                    '''enable RAM mode (enacted by IO pulse) and fix other parameters:'''
                    self.DDS_ad9910_channel0.set_cfr1(internal_profile=0, ram_enable = 1, ram_destination=ad9910.RAM_DEST_FTW, manual_osk_external=0, osk_enable=1, select_auto_osk=0)
                    self.DDS_ad9910_channel0.sw.on()
                    self.DDS_ad9910_channel0.cpld.io_update.pulse_mu(8)


                if self.list_ttl4[i] == "on":
                    self.ttl_channel4.on()
                else:
                    self.ttl_channel4.off()
                    
                delay (100 * ns)
        
                if self.list_ttl5[i] == "on":
                    self.ttl_channel5.on()
                else:
                    self.ttl_channel5.off()            
                    
                delay (100 * ns)
                
                
                if self.list_ttl6[i] == "on":
                    self.ttl_channel6.on()
                else:
                    self.ttl_channel6.off()
                
                delay (100 * ns)
                
                if self.list_ttl7[i] == "on":
                    self.ttl_channel7.on()
                else:
                    self.ttl_channel7.off()
                
                delay (100 * ns)
                
                if self.list_ttl8[i] == "on":
                    self.ttl_channel8.on()
                else:
                    self.ttl_channel8.off()
  
                delay (100 * ns)
                
                if self.list_ttl9[i] == "on":
                    self.ttl_channel9.on()
                else:
                    self.ttl_channel9.off()
            
                delay (100 * ns)
                
                if self.list_ttl10[i] == "on":
                    self.ttl_channel10.on()
                else:
                    self.ttl_channel10.off()
                    
                    
                delay (100 * ns)
                
                
                if self.list_ttl11[i] == "on":
                    self.ttl_channel11.on()
                else:
                    self.ttl_channel11.off()
        
        
        
                delay (100 * ns)
                
                
                if self.list_ttl12[i] == "on":
                    self.ttl_channel12.on()
                else:
                    self.ttl_channel12.off()
        
        
                delay (100 * ns)
                
                
                if self.list_ttl13[i] == "on":
                    self.ttl_channel13.on()
                else:
                    self.ttl_channel13.off()
        
        
                delay (100 * ns)
                
                if self.list_ttl14[i] == "on":
                    self.ttl_channel14.on()
                else:
                    self.ttl_channel14.off()
        
                delay (100 * ns)
                
                if self.list_ttl15[i] == "on":
                    self.ttl_channel15.on()
                else:
                    self.ttl_channel15.off()
        
                    # self.DDS_ad9910_channel0.sw.on()
                    # self.DDS_ad9910_channel1.sw.on()
                    # self.DDS_ad9910_channel2.sw.on()
                    # self.DDS_ad9910_channel3.sw.on()
        
                    # self.DDS_ad9912_channel0.sw.on()
                    # self.DDS_ad9912_channel1.sw.on()
                    # self.DDS_ad9912_channel2.sw.on()
                    # self.DDS_ad9912_channel3.sw.on()
        
                    # self.zotino0.set_dac(self.list_voltages[i], self.list_of_dac_channels)
            
                # print(self.array_amplitude_time[i], "print(self.array_amplitude_time[i]")
                # print(self.array_channel_time[i], "self.array_channel_time[i]")
                # # with parallel:
                # print(self.list_of_combined_amplitude_coloumn[i], "self.list_of_combined_amplitude_coloumn[i]")  
                # self.DDS_ad9910_channel0.set(50.0 * MHz, amplitude = self.list_ad9910_channel0_amp[i])
                # print("past this point")
                
                if self.list_of_zotino_ramp_selector[i] == 1:
                    for u in range(len(self.list_of_updated_voltages)):
                        self.zotino0.write_dac(self.list_of_dac_channels[i][u], self.list_of_updated_voltages[i][u])
                        self.zotino0.load()
                        # delay(1 * us)
                        

                else:
                    for u in range(len(self.list_voltages)):
                        self.zotino0.write_dac(self.list_of_dac_channels[i][u], self.list_voltages[i][u])
                        self.zotino0.load()
                        # delay(1 * us)
                        
          
                if self.list_of_amplitude_modulation_selector[i] == 1:
                    
                    if self.list_parameter_ch0[i] == 2:
                        self.DDS_ad9910_channel0.set_cfr1(ram_enable=0)
                        self.DDS_ad9910_channel0.cpld.io_update.pulse(100*ns)
                        self.DDS_ad9910_channel0.set_att(self.list_ad9910_channel0_atten[i])
                        delay(1 * us)
                        self.DDS_ad9910_channel0.set(self.list_ad9910_channel0_freq[i] * MHz, amplitude = 1.0)

                    if self.list_parameter_ch1[i] == 2:
                        self.DDS_ad9910_channel1.set_cfr1(ram_enable=0)
                        self.DDS_ad9910_channel1.cpld.io_update.pulse(100*ns)
                        self.DDS_ad9910_channel1.set_att(self.list_ad9910_channel1_atten[i])
                        delay(1 * us)
                        self.DDS_ad9910_channel1.set(self.list_ad9910_channel1_freq[i] * MHz, amplitude = 1.0)
                    
                    if self.list_parameter_ch2[i] == 2:
                        self.DDS_ad9910_channel2.set_cfr1(ram_enable=0)
                        self.DDS_ad9910_channel2.cpld.io_update.pulse(100*ns)
                        self.DDS_ad9910_channel2.set_att(self.list_ad9910_channel2_atten[i])
                        delay(1 * us)
                        self.DDS_ad9910_channel2.set(self.list_ad9910_channel2_freq[i] * MHz, amplitude = 1.0)
                    
                    if self.list_parameter_ch3[i] == 2:
                        self.DDS_ad9910_channel3.set_cfr1(ram_enable=0)
                        self.DDS_ad9910_channel3.cpld.io_update.pulse(100*ns)
                        self.DDS_ad9910_channel3.set_att(self.list_ad9910_channel3_atten[i])
                        delay(1 * us)
                        self.DDS_ad9910_channel3.set(self.list_ad9910_channel3_freq[i] * MHz, amplitude = 1.0)


                    kk4 = 0
                    for entry15 in self.final_time_list[i]:
                        if self.final_channel_list[i][kk4] == 3.01:
                            self.DDS_ad9910_channel3.set(self.list_ad9910_channel3_freq[i] * MHz, amplitude = self.final_voltage_list[i][kk4])
                        if self.final_channel_list[i][kk4] == 2.01:
                            self.DDS_ad9910_channel2.set(self.list_ad9910_channel2_freq[i] * MHz, amplitude = self.final_voltage_list[i][kk4])
                        if self.final_channel_list[i][kk4] == 1.01:
                            self.DDS_ad9910_channel1.set(self.list_ad9910_channel1_freq[i] * MHz, amplitude = self.final_voltage_list[i][kk4])
                        if self.final_channel_list[i][kk4] == 0.01:
                            self.DDS_ad9910_channel0.set(self.list_ad9910_channel0_freq[i] * MHz, amplitude = self.final_voltage_list[i][kk4])
                        if self.final_channel_list[i][kk4] == 0.0:
                            self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                            self.zotino0.load()
                        if self.final_channel_list[i][kk4] == 1.0:
                            self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                            self.zotino0.load()
                        if self.final_channel_list[i][kk4] == 2.0:
                            self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                            self.zotino0.load()
                        if self.final_channel_list[i][kk4] == 3.0:
                            self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                            self.zotino0.load()
                        if self.final_channel_list[i][kk4] == 4.0:
                            self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                            self.zotino0.load()
                        if self.final_channel_list[i][kk4] == 5.0:
                            self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                            self.zotino0.load()
                        if self.final_channel_list[i][kk4] == 6.0:
                            self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                            self.zotino0.load()
                        if self.final_channel_list[i][kk4] == 7.0:
                            self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                            self.zotino0.load()
                        if self.final_channel_list[i][kk4] == 8.0:
                            self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                            self.zotino0.load()
                        if self.final_channel_list[i][kk4] == 9.0:
                            self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                            self.zotino0.load()
                        if self.final_channel_list[i][kk4] == 10.0:
                            self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                            self.zotino0.load()
                        if self.final_channel_list[i][kk4] == 11.0:
                            self.zotino0.write_dac(np.int32(self.final_channel_list[i][kk4]), self.final_voltage_list[i][kk4])
                            self.zotino0.load()
                            
                        # print(now_mu()-t00, "execuetion time")
                        delay(self.final_time_list[i][kk4] * ns)
                        kk4 = kk4 + 1
                        
                        
    
                self.sampler0.sample(self.list_of_sampler_values[i])



                delay((self.list_t_duration[i] * ns) - (now_mu()-t0)*ns)`

lriesebos

han94ros the information you provided does not allow me to understand at what exact line the underflow happens. Regardless, it is likely that you will have an underflow exception during the second "active stage" loop. You add 1 second of slack at the beginning of the kernel, which is probably enough for the first "active stage" loop. At the end of that loop, you sample your ADC's, which will result in negative slack. In the last line of your kernel, you add a delay which could give you positive slack again if large enough, but if not, you will experience an underflow exception at the start of the second loop. You will need to make sure to regain slack after every iteration, increasing the existing 1 second slack at the start of your kernel outside of the loop will not help.

han94ros

This is the error I am getting, would increasing the SED lanes aid this or is this a limitation of the number of SPI buses per device.

[ 306.109062s] INFO(runtime::kern_hwreq): resetting RTIO [ 307.368904s] DEBUG(runtime::session): comm<-kern RunException { exception: Exception { name: "0:artiq.coredevice.exceptions.RTIOUnderflow", file: "ksupport/rtio.rs", line: 67, column: 13, function: "(Rust function)", message: "RTIO underflow at {0} mu, channel {1}, slack {2} mu", param: [303999475992, 29, -19120] }, backtrace: [42364, 18012, 10056] } [ 307.369967s] DEBUG(runtime::session): comm->host KernelException { name: "0:artiq.coredevice.exceptions.RTIOUnderflow", message: "RTIO underflow at {0} mu, channel {1}, slack {2} mu", param: [303999475992, 29, -19120], file: "ksupport/rtio.rs", line: 67, column: 13, function: "(Rust function)", backtrace: [42364, 18012, 10056] } [ 307.405087s] INFO(runtime::session): no connection, starting idle kernel [ 307.411012s] INFO(runtime::session): no idle kernel found [ 309.418631s] INFO(runtime::mgmt): new connection from 10.34.16.101:57860

sb10q

han94ros would increasing the SED lanes aid this

No.
Increasing the number of SED lanes only helps with sequence errors, and never helps with any other problem.

han94ros

lriesebos Thanks for the reply. The issue is that I need to run these iterations (active stages) successively without delay. Each stage needs to run for example for 200ms and the whole sequence of stages needs to run within the desired time (back to back), therefore I had gone for a single kernel as you had suggested. I cannot therefore place a delay within each stage/loop iteration. Do you believe I would have no choice but to introduce this delay, roughly in the span of microseconds?

lriesebos

han94ros First of all, you will need to confirm that my hypothesis is correct. If that is the case, then you could try one of the following ideas. The current driver of the sampler does not seem to provide direct control of buffering (i.e. scheduling the sampling on a timestamp and recovering the results at a later time). If possible you could try to modify the driver such that it does, allowing you to not lose all slack when sampling. Alternatively, you could modify the code to first schedule all DDS operations without sampling, revert the timeline, and then schedule only the sampling operations at the right time. You will need a large amount of initial slack to do this kind of timeline reversing.

han94ros

lriesebos You were absolutely bang on about the ADC creating the negative slack! I have measured the slack after each operation and there is a dramatic decrease in the slack after the ADC sampling at the end.

INFO:worker(7397,Modulation_frequency_test_129.py):print:1154110192 slack 12 INFO:worker(7397,Modulation_frequency_test_129.py):print:-118192 slack 1

Have you seen examples of this type of timeline reversing.

han94ros

lriesebos would timeline_reversing simply involve using at_mu

han94ros

@sb10q Would the modification of the driver to provide direct control of buffering be a difficult task, could you please advise me on how I could go about this?

lriesebos

han94ros Yes, at_mu() is probably what you will use to revert the timeline to earlier decided timestamps allowing you to schedule the sampling operations after all DDS operations are scheduled. I do not have a ready-made example for you at this moment.

han94ros

lriesebos No thats fine, thanks for the confirmation.

han94ros

I have saved all the output signals (DDS, Analog and TTL) using the DMA and I am able to play this back correctly within a given period for each stage. Unfortunately I also need to include the sampler in each stage and this is causing RTIO underflow issues as the RTIO wall clock and the kernel timeline cursor are being brought to the same point. I have been advised to revert the timeline using at_mu and then schedule the sampler. However even while doing this I have not been able to remove the underflow error. I have been trying to integrate the sampler in the main script for the last two weeks, with and without the use of the DMA to save the output signals, but neither method has been successful. Please find the snippet of the relevant section of the code attached. I would really appreciate advice on this as this is the last section required to get the entire system running and I have been stuck on this for two weeks.

        
        
    @kernel
def run(self):
    self.core.reset()
    self.record()
    for m in self.list_of_active_stages:
        
        self.list_of_pulses_handle[m] = self.core_dma.get_handle(self.list_of_stages[m])
        print(self.list_of_pulses_handle, "yes")
        
    
    delay(2 *s)
    # self.core.break_realtime()
        
    for h in range(self.number_of_repetitions):
        # i = 0 
        # i = np.int64(i)
        for i in self.list_of_active_stages:
            
            t0 = now_mu()
        
            self.core_dma.playback_handle(self.list_of_pulses_handle[i])
            self.list_of_t1[i] = now_mu()
            
            


            delay((self.list_t_duration[i] * ns) - (now_mu()-t0)*ns )

    
    delay(5 * s)      
    for hh in range(self.number_of_repetitions):
        
        for ii in self.list_of_active_stages:
            

            at_mu(self.list_of_t1[ii])
            self.sampler0.sample(self.list_of_sampler_values[ii])

han94ros

Can someone please explain the difference between
delay((self.list_t_duration[i] * ns) - (now_mu()-t0)*ns )
and

t1 = now_mu()
delay((self.list_t_duration[i] * ns) - (t1-t0)*ns )

The latter is allowing my script to work whereas the former is not. Is it an issue with recursion with python/artiq?
This is allowing the original script to work without the use of timeline reversal and the inclusion of the sampler. I can run the script down to 300*us given the slack of sampler0.sample being roughly 100us. Can someone explain this using time concepts.

lriesebos

han94ros Does that mean your code is working as expected at this moment?

For the two different code snippets: your conversions are not that great, which might cause unexpected issues with 32/64 bit integer casting. Timestamps (such as returned by now_mu()) are in machine units (int64) and should be used with delay_mu(). If you want to convert them to seconds for using with delay(), use self.core.mu_to_seconds().

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