Cannot set DDS after RAM ramp

jonhood

I am using the ad9910 profiles to ramp, but afterwards setting amplitude with set() doesn't work. My code is below. Any ideas?

from artiq.experiment import *                                             
from artiq.coredevice.ad9910 import (RAM_DEST_ASF, RAM_MODE_BIDIR_RAMP, RAM_MODE_RAMPUP)

class simple_example2(EnvExperiment):
    def build(self): 
        self.setattr_device("core")                                       
        self.dds = self.get_device("urukul2_ch2")                           
        self.ttl0 = self.get_device("ttl0")  
    @kernel 
    def run(self):
        self.core.break_realtime()
        delay(100*ms)
        self.ttl0.output()
        self.dds.cpld.init() 
        self.dds.init()              
        self.dds.sw.on()    
        delay(100*ms)
        self.profile0_set()
        
        print("Starting loop")                                                                    
        for i in range(1000):  
            delay(1*ms)
            self.dds.cpld.set_profile(0) 
            delay(100*ms)
            self.dds.cpld.set_profile(1)
            delay(100*ms) 
            self.dds.set(1*MHz, amplitude = 1.0) # This command does not do anything.
            self.ttl0.pulse(10*us)
        
        
    @kernel
    def profile0_set(self):
        data_ram = [-262144, -43253760, -86245376, -128974848, -171966464, -214958080, -257949696, -300941312, -343932928, -386662400, -429654016, -472645632, 
        -515637248, -558628864, -601620480, -644349952, -687341568, -730333184, -773324800, -816316416, -859308032, -902037504, -945029120, -988020736, -1031012352,
        -1074003968, -1116995584, -1159725056, -1202716672, -1245708288, -1288699904, -1331691520, -1374683136, -1417412608, -1460404224, -1503395840, -1546387456,
        -1589379072, -1632370688, -1675100160, -1718091776, -1761083392, -1804075008, -1847066624, -1890058240, -1932787712, -1975779328, -2018770944, -2061762560,
        -2104754176, -2147483648, 2104492032, 2061500416, 2018508800, 1975517184, 1932525568, 1889796096, 1846804480, 1803812864, 1760821248, 1717829632, 1674838016, 
        1632108544, 1589116928, 1546125312, 1503133696, 1460142080, 1417150464, 1374420992, 1331429376, 1288437760, 1245446144, 1202454528, 1159462912, 1116733440,
        1073741824, 1030750208, 987758592, 944766976, 901775360, 859045888, 816054272, 773062656, 730071040, 687079424, 644087808, 601358336, 558366720, 515375104, 
        472383488, 429391872, 386400256, 343670784, 300679168, 257687552, 214695936, 171704320, 128712704, 85983232, 42991616] # This corresponds to a 100 point scan between 1.0 and 0.0 in mu
       
        self.dds.cpld.set_profile(0)
        self.dds.set_profile_ram(start=0 , end=0 + len(data_ram) - 1,step=250,profile=0,mode=RAM_MODE_BIDIR_RAMP)  
        self.dds.cpld.io_update.pulse_mu(8)
        delay(10*ms)
        self.dds.write_ram(data_ram)  
        delay(5*ms) 
        self.dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)         
        self.dds.set_frequency(1*MHz)                                        
        self.dds.cpld.io_update.pulse_mu(8)                                   
        self.dds.set_att(10*dB)

sb10q

Use self.dds.set(1*MHz, amplitude = 1.0, profile=1)

jonhood

Thank you sb10q . In a related problem, I am trying to switch between two RAMP_UP profiles, but set_profile(1) does not do anything. A simplified code is below. We have been trying to fix it all day.

from artiq.experiment import *                                             
from artiq.coredevice.ad9910 import (RAM_DEST_ASF, RAM_MODE_RAMPUP, RAM_MODE_RAMPUP)

class simple_example3(EnvExperiment):
    def build(self): 
        self.setattr_device("core")                                       
        self.dds = self.get_device("urukul2_ch2")                           
        self.ttl0 = self.get_device("ttl0")  
    @kernel 
    def run(self):
        self.core.break_realtime()
        delay(100*ms)
        self.ttl0.output()
        self.dds.cpld.init() 
        self.dds.init()              
        self.dds.sw.on()    
        delay(100*ms)
        self.profile0_set()
        self.profile1_set()
        
        print("Starting loop")                                                                    
        for i in range(1000):  
            delay(1*ms)
            self.dds.cpld.set_profile(0) 
            delay(100*ms)
            self.dds.cpld.set_profile(1) # does not do anything
            delay(100*ms)                  
            self.ttl0.pulse(10*us)
        
        
    @kernel
    def profile0_set(self):
        data_ram = [-262144, -43253760, -86245376, -128974848, -171966464, -214958080, -257949696, -300941312, -343932928, -386662400, -429654016, -472645632, 
        -515637248, -558628864, -601620480, -644349952, -687341568, -730333184, -773324800, -816316416, -859308032, -902037504, -945029120, -988020736, -1031012352,
        -1074003968, -1116995584, -1159725056, -1202716672, -1245708288, -1288699904, -1331691520, -1374683136, -1417412608, -1460404224, -1503395840, -1546387456,
        -1589379072, -1632370688, -1675100160, -1718091776, -1761083392, -1804075008, -1847066624, -1890058240, -1932787712, -1975779328, -2018770944, -2061762560,
        -2104754176, -2147483648, 2104492032, 2061500416, 2018508800, 1975517184, 1932525568, 1889796096, 1846804480, 1803812864, 1760821248, 1717829632, 1674838016, 
        1632108544, 1589116928, 1546125312, 1503133696, 1460142080, 1417150464, 1374420992, 1331429376, 1288437760, 1245446144, 1202454528, 1159462912, 1116733440,
        1073741824, 1030750208, 987758592, 944766976, 901775360, 859045888, 816054272, 773062656, 730071040, 687079424, 644087808, 601358336, 558366720, 515375104, 
        472383488, 429391872, 386400256, 343670784, 300679168, 257687552, 214695936, 171704320, 128712704, 85983232, 42991616] # This corresponds to a 100 point scan between 1.0 and 0.0 in mu
       
        self.dds.cpld.set_profile(0)
        self.dds.set_profile_ram(start=0 , end=0 + len(data_ram) - 1,step=250,profile=0,mode=RAM_MODE_RAMPUP)  
        self.dds.cpld.io_update.pulse_mu(8)
        delay(10*ms)
        self.dds.write_ram(data_ram)  
        delay(5*ms) 
        self.dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)         
        self.dds.set_frequency(1*MHz)                                        
        self.dds.cpld.io_update.pulse_mu(8)                                   
        self.dds.set_att(10*dB)  
        
    @kernel
    def profile1_set(self):
        data_ram = [42991616, 85983232, 128712704, 171704320, 214695936, 257687552, 300679168, 343670784, 386400256, 429391872, 472383488, 515375104, 558366720,
        601358336, 644087808, 687079424, 730071040, 773062656, 816054272, 859045888, 901775360, 944766976, 987758592, 1030750208, 1073741824, 1116733440, 1159462912,
        1202454528, 1245446144, 1288437760, 1331429376, 1374420992, 1417150464, 1460142080, 1503133696, 1546125312, 1589116928, 1632108544, 1674838016, 1717829632,
        1760821248, 1803812864, 1846804480, 1889796096, 1932525568, 1975517184, 2018508800, 2061500416, 2104492032, -2147483648, -2104754176, -2061762560, -2018770944,
        -1975779328, -1932787712, -1890058240, -1847066624, -1804075008, -1761083392, -1718091776, -1675100160, -1632370688, -1589379072, -1546387456, -1503395840,
        -1460404224, -1417412608, -1374683136, -1331691520, -1288699904, -1245708288, -1202716672, -1159725056, -1116995584, -1074003968, -1031012352, -988020736,
        -945029120, -902037504, -859308032, -816316416, -773324800, -730333184, -687341568, -644349952, -601620480, -558628864, -515637248, -472645632, -429654016,
        -386662400, -343932928, -300941312, -257949696, -214958080, -171966464, -128974848, -86245376, -43253760, -262144] # This corresponds to a 100 point scan between 0.0 and 1.0 in mu
       
        self.dds.cpld.set_profile(1)
        self.dds.set_profile_ram(start=0 , end=0 + len(data_ram) - 1,step=250,profile=1,mode=RAM_MODE_RAMPUP)   
        self.dds.cpld.io_update.pulse_mu(8)
        delay(10*ms)
        self.dds.write_ram(data_ram)  
        delay(5*ms) 
        self.dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)         
        self.dds.set_frequency(1*MHz)                                        
        self.dds.cpld.io_update.pulse_mu(8)                                  
        self.dds.set_att(10*dB)

sb10q

Same, use set_profile_ram(... profile=1)

dpeana

sb10q How would we implement that differently than the code above? The code above gives either no signal at all when both profiles are used or a single profile’s ramp when only one profile is used at a time (i.e. profile1_set() and set_profile(1) are commented).

han94ros

dpeana If you are using several profiles on the same cpld of a AD9910 channel then you may need to disable the RAM in between to allow for writing e.g ram_enable=0. Otherwise a simpler solution would be to write all the data to all the profiles before enabling the RAM.

dpeana

@sb10q I video called with han94ros earlier and we couldnt figure it out including attempting the fix he posted about immediately above. I tried what you recommended by doing set(...,profile = i) and it did not solve the problem. Do you have any other recommendations?

sb10q

Could it be that you are overwriting the RAM contents in profile1_set? You set the start address to 0 in both cases in the set_profile_ram call.

sb10q

See the AD9910 datasheet:

You need to partition the RAM (i.e. define appropriate addresses) yourself.

han94ros

sb10q I think we tried that in the video call, @dpeana is my other amplitude modulation script working? If it is can you try it again but with commenting out the repeated profile sets