M-Labs wrote a simple tool called microscope for debugging Migen running on silicon. I'm looking for example code illustrating it's use with eg Kasli v2 -- emphasis on setting up serial monitoring and clock. Here's an example of a simple module that would be interesting to instrument.

artiq/gateware/drtio/wrpll/ddmtd/DDMTDDeglitcherFirstEdge

Since serial interfaces are inherently slow is the intended use case a snail-paced clock (eg 10 kHz) so that the UART can easily keep up?

No, it supports using a trigger and buffer.

    a month later

    sb10q I have altered demo.py in Microscope to run on kasli v2.0, but I am getting no response using microscope.py. Here's the modified portion of the demo that I am working with:

    def main():
    platform = kasli.Platform("v2.0")
    top = MicroscopeDemo(platform.request("serial"), platform.default_clk_period)
    clock = platform.request("clk125_gtp")
    top.submodules += CRG(clock)
    platform.build(top)

    I would have stuck with the original platform.default_clk_name value, but kasli v2.0 doesn't support clk50 in its io. The command I am using for flashing is: artiq_flash --srcbuil -t kasli -V build -d ../microscope gateware. Also is the serial port that Microscope uses the same that the Misoc boot loader uses?

      I don't know what your CRG does, in any case you should set the period according to the output of that CRG, platform.default_clk_period may or may not be equal to it.

      We are using Kasli v2.0.

      clock = platform.request(platform.default_clk_name)

      For Kasli v2.0 clk50 is not defined. What should the value of default_clk_name be?

      It goes through the GT and needs a special buffer. You need manual clocking.

        Looking at the Kasli 2 schematics I see that the default 125 MHz XO (OSC2 in schematic) is routed to MGTREFCLK1 on the FPGA which is part of the gigabit transceiver silicon. I translate what you said to mean that the microscope doesn't configure the transceiver so the Microscope is left without a clock. In contrast the front panel SMA is routed to ordinary clock-capable FPGA pins labeled sma_clkin in Migen.

        Please tell us verbatim the minimal source that enables Microscope for Kasli 2. I'll make a patch for the repository. -Joe

        sb10q What do you mean by manual clocking? For reference the device under test is still unresponsive after trying to replicate the default clock, 50 MHz, over sma_clkin when flashed with this code:
        `
        from migen import *
        from migen.build.platforms.sinara import kasli
        from migen.genlib.io import CRG

        from microscope import *

        class MicroscopeDemo(Module):
        def init(self, serial_pads, sys_clk_freq):
        counter = Signal(32)
        toggle1 = Signal()
        toggle2 = Signal()
        self.comb += [
        toggle1.eq(counter[29]),
        toggle2.eq(counter[28])
        ]
        self.sync += counter.eq(counter + 1)

            self.submodules += [
        add_probe_single("demo", "toggle1", toggle1),
        add_probe_single("demo", "toggle2", toggle2),
        add_probe_buffer("demo", "counter", counter)
    ]

    self.submodules += Microscope(serial_pads, sys_clk_freq)

        def main():
        platform = kasli.Platform("v2.0")
        top = MicroscopeDemo(platform.request("serial"), 1e9/20)
        clock = platform.request("sma_clkin")
        top.submodules += CRG(clock)
        platform.build(top)

        if name == "main":
        main()`

          "Manual clocking" means reimplementing the Migen CRG with tweaks such as using the special GTP clock input buffer to drive the clock domain.

          I don't know why it doesn't work with the SMA, but 1e9/20 looks suspicious considering you passed a period before.

          Try blinking an LED first to validate clocking perhaps?

          6 days later

          Thanks for the explanation and the great suggestion, unfortunately here's the result. Is there a way around this?