riscv core not supported in Artiq beta

melanieAQ

I mistakenly modified the Artiq installation on my Linux host to Artiq-6 and today I changed it back to the current Artiq beta via the directions on this page. However, when I run a simple experiment, the initialization of "core" fails because "riscv" is not a recognized target. What is the remedy? I would like to be able to make modifications to the artiq compiler, so I need our core to be supported. Again, thanks for your support! --Melanie

Here is the trace:

ARTIQ v7.7898.311a818a.beta

[nix-shell:~]$ artiq_run -v --device-db ~/device_db.py big.py
Traceback (most recent call last):
  File "/nix/store/nwagsxrhbgn77347w7al33bd3w58knqq-python3-3.8.11-env/lib/python3.8/site-packages/artiq/master/worker_db.py", line 91, in get
    dev = _create_device(desc, self)
  File "/nix/store/nwagsxrhbgn77347w7al33bd3w58knqq-python3-3.8.11-env/lib/python3.8/site-packages/artiq/master/worker_db.py", line 30, in _create_device
    return device_class(device_mgr, **desc.get("arguments", {}))
  File "/nix/store/nwagsxrhbgn77347w7al33bd3w58knqq-python3-3.8.11-env/lib/python3.8/site-packages/artiq/coredevice/core.py", line 84, in __init__
    raise ValueError("Unsupported target")
ValueError: Unsupported target

Here is the core description from our device_db.py:

# Autogenerated for the aq variant
core_addr = "192.168.1.75"

device_db = {
    "core": {
        "type": "local",
        "module": "artiq.coredevice.core",
        "class": "Core",
        "arguments": {"host": core_addr, "ref_period": 1e-09,  "target": "riscv"},
    },

sb10q

Regenerate the device database, there are two possible strings depending whether the FPU is present or not.

melanieAQ

With some searching I found via this wiki I can regenerate the device database like this:
python artiq/frontend/artiq_ddb_template.py ~/aq.json

And I found our variant aq.json catalogued here

I also had to modify artiq/flake.nix to include jsonschema like this

         nativeBuildInputs = [ pkgs.qt5.wrapQtAppsHook ];
         # keep llvm_x and lld_x in sync with llvmlite
         propagatedBuildInputs = [ pkgs.llvm_11 pkgs.lld_11 llvmlite-new sipyco pythonparser ]
-          ++ (with pkgs.python3Packages; [ pyqtgraph pygit2 numpy dateutil scipy prettytable pyserial python-Levenshtein h5py pyqt5 qasync ]);
+          ++ (with pkgs.python3Packages; [ pyqtgraph pygit2 jsonschema numpy dateutil scipy prettytable pyserial python-Levenshtein h5py pyqt5 qasync ]);
 
         dontWrapQtApps = true;
         postFixup = ''

Now my device database has rv32g instead of riscv. (I thought our core does not have FPU but I could be wrong about that. ima implies no FPU correct?)

All set for now. --Melanie

sb10q

melanieAQ I also had to modify artiq/flake.nix to include jsonschema like this

If you use nix develop then jsonschema is already included.