ARTIQ-5 is released today. To update, follow the stable branch manual at https://m-labs.hk/artiq/manual/installing.html.

Highlights of this new release (compared to 4.0):

  • Performance improvements:
  • Improved packaging and build system:
    • new continuous integration/delivery infrastructure based on Nix and Hydra,
      providing reproducibility, speed and independence.
    • rolling release process (https://github.com/m-labs/artiq/issues/1326).
    • firmware, gateware and device database templates are automatically built for all
      supported Kasli variants.
    • new JSON description format for generic Kasli systems.
    • Nix packages are now supported.
    • many Conda problems worked around.
    • controllers are now out-of-tree.
    • split packages that enable lightweight applications that communicate with ARTIQ,
      e.g. controllers running on non-x86 single-board computers.
  • Improved Urukul support:
    • AD9910 RAM mode.
    • Configurable refclk divider and PLL bypass.
    • More reliable phase synchronization at high sample rates.
    • Synchronization calibration data can be read from EEPROM.
  • A gateware-level input edge counter has been added, which offers higher
    throughput and increased flexibility over the usual TTL input PHYs where
    edge timestamps are not required. See artiq.coredevice.edge_counter for
    the core device driver and artiq.gateware.rtio.phy.edge_counter/
    artiq.gateware.eem.DIO.add_std for the gateware components.
  • With DRTIO, Siphaser uses a better calibration mechanism.
    See: https://github.com/m-labs/artiq/commit/cc58318500ecfa537abf24127f2c22e8fe66e0f8
  • Schedule updates can be sent to influxdb (artiq_influxdb_schedule).
  • Experiments can now programatically set their default pipeline, priority, and flush flag.
  • List datasets can now be efficiently appended to from experiments using
    artiq.language.environment.HasEnvironment.append_to_dataset.
  • The core device now supports IPv6.
  • To make development easier, the bootloader can receive firmware and secondary FPGA
    gateware from the network.
  • Python 3.7 compatibility (Nix and source builds only, no Conda).
  • Various other bugs from 4.0 fixed.
  • Preliminary Sayma v2 and Metlino hardware support.

Breaking changes:

  • The artiq.coredevice.ad9910.AD9910 and
    artiq.coredevice.ad9914.AD9914 phase reference timestamp parameters
    have been renamed to ref_time_mu for consistency, as they are in machine
    units.
  • The controller manager now ignores device database entries without the
    "command" key set to facilitate sharing of devices between multiple
    masters.
  • The meaning of the -d/--dir and --srcbuild options of artiq_flash
    has changed.
  • Controllers for third-party devices are now out-of-tree.
  • aqctl_corelog now filters log messages below the WARNING level by default.
    This behavior can be changed using the -v and -q options like the other
    programs.
  • On Kasli the firmware now starts with a unique default MAC address
    from EEPROM if mac is absent from the flash config.
  • The -e/--experiment switch of artiq_run and artiq_compile
    has been renamed -c/--class-name.
  • artiq_devtool has been removed.
  • Much of artiq.protocols has been moved to a separate package sipyco.
    artiq_rpctool has been renamed to sipyco_rpctool.
  • artiq_ctlmgr and the influxdb tools have moved to a separate package artiq-comtools (normally installed by default).