I upgrade the flash in KASLI to add DIO TTL cards. Everything looks no problem but except for phaser.
I tested my phaser with the script "artiq_sinara_tester -o phasers", and the test fails with an exception error "invalid board id". It seems somehow the saved id number for phaser isn't "19" as nominated.

To be helped, I reveal my development environment and the process I took for flashing.

[Environment]

  • Ubuntu
  • ARTIQ was installed by "flake.nix" in GitHub ARTIQ release-7.

[hardware description json]
{
"target": "kasli",
"min_artiq_version": "7.0",
"variant": "kriss2",
"hw_rev": "v2.0",
"ext_ref_frequency": 10e6,
"base": "standalone",
"core_addr": "192.168.1.75",
"peripherals": [
{
"type": "dio",
"board": "DIO_SMA",
"ports": [1],
"bank_direction_low": "input",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_SMA",
"ports": [2],
"bank_direction_low": "input",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_MCX",
"ports": [3],
"bank_direction_low": "input",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_MCX",
"ports": [4],
"bank_direction_low": "input",
"bank_direction_high": "output"
},
{
"type": "urukul",
"dds": "ad9910",
"ports": [5, 6],
"clk_sel": 2,
"synchronization": true
},
{
"type": "phaser",
"ports": [7]
},
{
"type": "sampler",
"hw_rev": "v2.3",
"ports": [10, 11]
}
]
}

[Processes]
$ git clone [m-labs git repository] --branch release-7
$ cd artiq && nix develop && cd ..
$ python -m artiq.gateware.targetss.kasli_generic kriss2.json
$ artiq_flash --src-build -d artiq_kasli/kriss2

[Boot loading monitoring : flterm ttyUSB]
MiSoC Bootloader
Copyright (c) 2017-2022 M-Labs Limited

Bootloader CRC passed
Gateware ident 7.0.unknown;kriss2
Initializing SDRAM...
Read leveling scan:
Module 1:
00000000000011111111110000000000
Module 0:
00000000000111111111111000000000
Read leveling: 16+-5 16+-6 done
SDRAM initialized
Memory test passed

Booting from flash...
Starting firmware.
[ 0.000013s] INFO(runtime): ARTIQ runtime starting...
[ 0.003931s] INFO(runtime): software ident 7.0.unknown;kriss2
[ 0.009774s] INFO(runtime): gateware ident 7.0.unknown;kriss2
[ 0.015631s] INFO(runtime): log level set to INFO by default
[ 0.021353s] INFO(runtime): UART log level set to INFO by default
[ 0.172895s] INFO(runtime::rtio_clocking): using external RTIO clock with PLL bypass
[ 0.296990s] INFO(runtime::rtio_clocking::crg): Using internal RTIO clock
[ 0.328079s] INFO(runtime): network addresses: MAC=e8-eb-1b-45-d2-42 IPv4=192.168.1.75 IPv6-LL=fe80::eaeb:1bff:fe45:d242 IPv6=no configured address
[ 0.341852s] INFO(runtime::mgmt): management interface active
[ 0.354075s] INFO(runtime::session): accepting network sessions
[ 0.367151s] INFO(runtime::session): running startup kernel
[ 0.371613s] INFO(runtime::session): no startup kernel found
[ 0.377428s] INFO(runtime::session): no connection, starting idle kernel
[ 0.384252s] INFO(runtime::session): no idle kernel found

[Test Results]
$artiq_sinara_tester -o phasers

****** Sinara system tester ******

*** Testing Phaser DACs and 6 USER LEDs.
Frequencies:
phaser0 10+0 10+1 10+2 10+3 10+4 MHz
Traceback (most recent call last):
File "/nix/store/8571si8v752ik2n42xya608scmck1wjl-python3.9-artiq-7.0.unknown/bin/.artiq_sinara_tester-wrapped", line 9, in <module>
sys.exit(main())
File "/nix/store/06gb6v8lh20hpxlx10fgb92mg45xfq1k-python3-3.9.13-env/lib/python3.9/site-packages/artiq/frontend/artiq_sinara_tester.py", line 788, in main
experiment.run(tests)
File "/nix/store/06gb6v8lh20hpxlx10fgb92mg45xfq1k-python3-3.9.13-env/lib/python3.9/site-packages/artiq/frontend/artiq_sinara_tester.py", line 739, in run
getattr(self, f"test{name}")()
File "/nix/store/06gb6v8lh20hpxlx10fgb92mg45xfq1k-python3-3.9.13-env/lib/python3.9/site-packages/artiq/frontend/artiq_sinara_tester.py", line 612, in test_phasers
self.set_phaser_frequencies(card_dev, duc, osc)
File "/nix/store/06gb6v8lh20hpxlx10fgb92mg45xfq1k-python3-3.9.13-env/lib/python3.9/site-packages/artiq/language/core.py", line 54, in run_on_core
return getattr(self, arg).run(run_on_core, ((self,) + k_args), k_kwargs)
File "/nix/store/06gb6v8lh20hpxlx10fgb92mg45xfq1k-python3-3.9.13-env/lib/python3.9/site-packages/artiq/coredevice/core.py", line 140, in run
self.run_compiled(kernel_library, embedding_map, symbolizer, demangler)
File "/nix/store/06gb6v8lh20hpxlx10fgb92mg45xfq1k-python3-3.9.13-env/lib/python3.9/site-packages/artiq/coredevice/core.py", line 130, in run_compiled
self.comm.serve(embedding_map, symbolizer, demangler)
File "/nix/store/06gb6v8lh20hpxlx10fgb92mg45xfq1k-python3-3.9.13-env/lib/python3.9/site-packages/artiq/coredevice/comm_kernel.py", line 716, in serve
self.serve_exception(embedding_map, symbolizer, demangler)
File "/nix/store/06gb6v8lh20hpxlx10fgb92mg45xfq1k-python3-3.9.13-env/lib/python3.9/site-packages/artiq/coredevice/comm_kernel.py", line 698, in _serve_exception
raise python_exn
ValueError: invalid board id

The same message appears when I use my phaser code (which worked before flashing).
Does anyone point out what I missed in the due process?

Thanks much,

    Hi hjlim , this error typically happens when the phaser is misconnected. Check that the cable from Phaser's EEM0 is connected to the respective Kasli's EEM port (7 in your case). Also you may have missed the artiq_ddb_template stage.
    Also I see that in your JSON you might have misconfigured the TTL. We usually set them all to the output except first 4 ports (bank_direction_low), but you can use them as in your device description. In any case, check that the switches are in the desired position: https://git.m-labs.hk/M-Labs/sinara-assembly/media/branch/master/src/img/ttl_mcx.jpg . This should not produce errors with Phaser, but you may have problems with your new TTLs.

      Thank you for paying attention on my post, and your kind advice on TTL setting.
      I am afraid that I have already checked EEM port number on KASLI and Phaser, and also took serious care about whether the related connectors were properly plugged.

      I am more afraid about what I haven't yet told.
      Before I upgrade KASLI flash, I flashed the STFT pulsegen gateware (QUARTIQ pulsegen) via the JTAG port on the Phaser board.
      But I only observed the board id error after I upgrade a KASLI flash.
      This error still stands even after I flashed back the phaser gateware to v0.5.

      But I will replace the cable and report here about results as your advice.

      Where is the JSON from? Are you taking ESD precautions while handling the hardware? Are you making sure that the hardware is powered down before handling EEM connectors?

        The problem was my clock settings. I had modified to use 125 MHz in clock distributers (Clocker).
        Uploading flashing, I returned 10 MHz as the original json describes. But this causes failure clock initialization and synch in phaser and this failure somehow blocks an internal phaser boot loading.

        I got hints when I tested Urukul by seeing that no "board id" problem but clock synch fails in Urukul with the 10 MHz clock. The major difference is the presence of FPGA in Phaser. And I thought there might not exist bypassing solution in phasor such as in KASLI.

        After I loaded 125 MHz in Clocker, and changed clock setting to 125 MHz in json, a phasor test is successfully passed.

        This help session is solved.
        Thank esavkin!

        sb10q

        Thank you for being interested! Mostly (...) I wear ESD band on my wrist.
        And I never mistake handling plugs while they are powered.