minimum input pulse length for ttl.timestamp_mu()?

Aawallin · May 28, 2019

Hi all, nice forum!

What is the minimum input pulse-length for ttl inputs?
In particular we are using a Hamamatsu PMT-counter and previously we stretched out the <10 ns long raw output of the PMT to about 100ns for our old counter system, like so: http://www.anderswallin.net/wp-content/uploads/2014/07/pulse_stretcher_test_PMT.png

could ARTIQ handle the raw PMT-output which is 10ns or a litte less in duration?

thanks!
Anders

sb10q · May 28, 2019

The minimum input pulse length for the gateware is one RTIO clock cycle, typically 8ns (could be less and down to 1ns, but I'd have to double-check the source to make sure that there is no mishandled corner case).
If you are using the DIO_SMA or DIO_BNC module, the isolator chip inside also has a minimum pulse width of 5ns, see https://www.silabs.com/documents/public/data-sheets/si865x-datasheet.pdf