Phase synchronization between Phaser Channels

claytonho

Hello,

Does anyone have any information on whether the latencies between the different phaser channels (i.e. channel 0 and channel 1) are deterministic?
I know that latencies between the oscillators within a channel are deterministic and that frames and sample times have to be aligned to, but so far I don't think anything I've read has explicitly talked about the latencies between the channels.

I'm testing this by setting oscillator0 on both channel 0 and channel 1 to 85 MHz and 0.999 amplitude.
Immediately before setting the oscillators, I align to a frame.
Every time the experiment is run, the phaser is completely reinitialized.

So far, I've tried the following in different combinations, and none seem to work:

leaving the oscillator phase accumulators cleared until I set them
setting a fixed fifo_offset for the phaser DAC (per the phaser documentation)
using dac_sync() before the oscillators are set
clearing both DUC phase accumulators and strobing them right before setting the oscillators

claytonho

Update - I think I sorted it out; was able to get a fixed phase delay between the different channel outputs each time.
The problem had to do with initializing the phaser each time I submitted the experiment.
After removing any phaser initialization and only setting the oscillator amplitude/phase, the phase delays between the channel outputs are fixed.

tommtommbom

Hello Clayton,

I am having a very similar problem as you where I am trying to get the same phase delay between the two phaser channels and make it deterministic. I've tried different things, specifically what you listed including:

introducing dac_sync() but it didn't help
changing the phase accumulator value to 0 or 1 in set_amplitude_phase()
no phaser init is done

but nothing seems to work. I was wondering what your solution was?

Here is an oscillioscope trace of the two signals which are offset from each other.

When I disable the phaser channels and renable them, the two signals on the scope are shifted differently. Do you have any suggestions for what to try?

For reference, here the is the python script I am running:

`
from artiq.experiment import *
import numpy as np
from set_center_remote import *

class PhaserTest(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("phaser0")
self.setattr_argument("phaser_attenuation", NumberValue(0, ndecimals=1, step=1))
self.setattr_argument("center_freq", NumberValue(300, ndecimals=0, step=100))
self.setattr_argument("DUC_freq", NumberValue(100, ndecimals=1, min=-200, max=200, step=10))
self.setattr_argument("enable_dac", BooleanValue(False))
self.setattr_argument("enable_phaser0_rf", BooleanValue(False))
self.setattr_argument("enable_phaser1_rf", BooleanValue(False))
self.setattr_argument("rf0_amplitude", NumberValue(0.1, ndecimals=3, min=0, max=1, step=0.1))
self.setattr_argument("rf1_amplitude", NumberValue(0.1, ndecimals=3, min=0, max=1, step=0.1))
self.setattr_argument("rf0_phase", NumberValue(0, ndecimals=2, min=-1, max=1, step=.25))
self.setattr_argument("rf1_phase", NumberValue(0, ndecimals=2, min=-1, max=1, step=.25))
def prepare(self):

    print('Preparing PhaserTest experiment...')

@kernel
def run(self):
    self.core.reset()
    # self.phaser0.init()
    # self.initializer.set_center_frequency()

    if self.enable_dac:
        self.phaser0.set_cfg(dac_txena=1)
    else:
        self.phaser0.set_cfg(dac_txena=0)


    if self.enable_phaser0_rf:
        self.enable_phaser_rf(channel=0, amplitude=self.rf0_amplitude, phase=self.rf0_phase)
    else:
        self.phaser0.channel[0].en_trf_out(rf=0, lo=0)

    if self.enable_phaser1_rf:
        self.enable_phaser_rf(channel=1, amplitude=self.rf1_amplitude, phase=self.rf1_phase)
    else:
        self.phaser0.channel[1].en_trf_out(rf=0, lo=0)


    at_mu(self.phaser0.get_next_frame_mu())
    with parallel:
        self.phaser0.channel[0].oscillator[0].set_amplitude_phase(amplitude=self.rf0_amplitude,
                                                                        phase=self.rf0_phase)
        self.phaser0.channel[1].oscillator[0].set_amplitude_phase(amplitude=self.rf1_amplitude,

                                                                        phase=self.rf1_phase)

    self.phaser0.dac_sync()


@kernel
def enable_phaser_rf(self, channel, amplitude, phase):
    self.phaser0.channel[channel].set_att(self.phaser_attenuation * dB)
    self.phaser0.channel[channel].set_duc_cfg()                   # set the digital upconverter
    self.phaser0.channel[channel].set_duc_frequency(self.DUC_freq * MHz)
    self.phaser0.duc_stb()
    self.phaser0.channel[channel].en_trf_out(rf=1, lo=0)
    self.core.break_realtime()
    # self.phaser0.channel[channel].oscillator[1].set_amplitude_phase(amplitude=0.0, phase=0.0, clr=1)`

claytonho

tommtommbom
Hey,

It looks like there are a few issues in getting determinate outputs here:

the key suspect here is use of "en_trf_out": "en_trf_out" powers down the RF output, which I believe causes the TRF phase to get shuffled
- if you want to disable any leakage outputs, you should go with an external switch instead of powering down the TRF
the DUC updates don't look deterministic - the DUC is cleared & set for each channel at different times without aligning to frames
- easiest way to fix this is to simply stage updates for both channels as you are, but call duc_stb once - this will latch changes to both channels at the same time

tommtommbom

Hello Clayton,

Thank you for the fast response!

I like your idea of an external switch (thank you for the suggestion!), but just to clarify, are you saying to keep the RF output of the phaser channels permanently on? I am worried about what happens when ARTIQ crashes or when I would need to turn off the phaser (to modify phaser code or settings). I would then have to remeasure and reconfigure the phase difference between the two channels. Or is there another way to turn off the phaser without losing phase coherence?