Hi,
I have problems getting the artiq_coreanalyzer to work properly. Following https://forum.m-labs.hk/d/188-analyzing-rtio-slack-with-gtkwave I've extracted the VCD file for different example experiments and I've opened them in GTKwave on windows 10. I can see the slack change during the experiment run and I believe that works as expected.
What doesn't work as expected are the ttl channel logs in the vcd file. When I select them in GTKwave I see a red bar and the value 'x' no matter which channel or which data format:

I can add additional log values using rtio_log and one of them is shown in the image. What additional steps do I need to take to automatically log the ttl values during the entire experiment?
Additionally, how do I log the zotino output values in a similar manner without calling rtio_log every time I change an analog output channel?

Help or pointers to additional resources would be greatly appreciated.

Best,
Malte

Are you submitting events to those TTL channels during the time the analyzer trace was taken?

    sb10q Yes, this sequence involves a handful of TTL events for each of these channels. I only added an rtio_log statement once in the beginning, which is on the lowest line in the pic. Not entirely sure if I need more rtio_log statements to catch the TTL events. Doesn't seem to be the case in the example. Other ideas?

      rtio_log has nothing to do with capturing TTL events, they should get captured with no rtio_log call at all. You also missed one part of my question: "...submitting... during the time the analyzer trace was taken". The RTIO analyzer records the events when they are submitted, not when the outputs switch, and the buffer has limited depth.

      Please also submit the experiment you used, VCD file, and raw analyzer buffer.

      8 days later

      Thanks for the debugging suggestions!
      Please don't assume that I "missed" that part of your question; I did misunderstand it apparently.

      The following is the easiest version of the code that I could do to reproduce the problem in a couple minutes:

      class VCD_TEST(EnvExperiment):
    def build(self):
        self.setattr_device("core")
        self.setattr_device("zotino0")

        self.setattr_device("ttl60")
    
    @kernel
    def run(self):
        self.core.reset()
        self.ttl60.on()
        self.zotino0.set_leds(16)
        
        delay(500*ms)
        self.zotino0.set_leds(5)
        
        delay(500*ms)

        self.ttl60.off()
        self.zotino0.set_leds(0)

      The VCD file looks like this:


      $timescale 1000ps $end
$scope module spi2/spi_mirny0 $end
$var wire 1 ! spi_mirny0/stb $end
$var wire 8 " spi_mirny0/flags $end
$var wire 5 # spi_mirny0/length $end
$var wire 8 $ spi_mirny0/div $end
$var wire 8 % spi_mirny0/chip_select $end
$var wire 32 & spi_mirny0/write $end
$var wire 32 ' spi_mirny0/read $end
$upscope $end
$scope module spi2/spi_urukul0 $end
$var wire 1 ( spi_urukul0/stb $end
$var wire 8 ) spi_urukul0/flags $end
$var wire 5 * spi_urukul0/length $end
$var wire 8 + spi_urukul0/div $end
$var wire 8 , spi_urukul0/chip_select $end
$var wire 32 - spi_urukul0/write $end
$var wire 32 . spi_urukul0/read $end
$upscope $end
$scope module spi2/spi_urukul1 $end
$var wire 1 / spi_urukul1/stb $end
$var wire 8 0 spi_urukul1/flags $end
$var wire 5 1 spi_urukul1/length $end
$var wire 8 2 spi_urukul1/div $end
$var wire 8 3 spi_urukul1/chip_select $end
$var wire 32 4 spi_urukul1/write $end
$var wire 32 5 spi_urukul1/read $end
$upscope $end
$scope module spi2/spi_zotino0 $end
$var wire 1 6 spi_zotino0/stb $end
$var wire 8 7 spi_zotino0/flags $end
$var wire 5 8 spi_zotino0/length $end
$var wire 8 9 spi_zotino0/div $end
$var wire 8 : spi_zotino0/chip_select $end
$var wire 32 ; spi_zotino0/write $end
$var wire 32 < spi_zotino0/read $end
$upscope $end
$scope module spi2/spi_zotino1 $end
$var wire 1 = spi_zotino1/stb $end
$var wire 8 > spi_zotino1/flags $end
$var wire 5 ? spi_zotino1/length $end
$var wire 8 @ spi_zotino1/div $end
$var wire 8 A spi_zotino1/chip_select $end
$var wire 32 B spi_zotino1/write $end
$var wire 32 C spi_zotino1/read $end
$upscope $end
$var wire 1 D ttl/ttl0 $end
$var wire 1 E ttl/ttl1 $end
$var wire 1 F ttl/ttl10 $end
$var wire 1 G ttl/ttl11 $end
$var wire 1 H ttl/ttl12 $end
$var wire 1 I ttl/ttl13 $end
$var wire 1 J ttl/ttl14 $end
$var wire 1 K ttl/ttl15 $end
$var wire 1 L ttl/ttl16 $end
$var wire 1 M ttl/ttl17 $end
$var wire 1 N ttl/ttl18 $end
$var wire 1 O ttl/ttl19 $end
$var wire 1 P ttl/ttl2 $end
$var wire 1 Q ttl/ttl20 $end
$var wire 1 R ttl/ttl21 $end
$var wire 1 S ttl/ttl22 $end
$var wire 1 T ttl/ttl23 $end
$var wire 1 U ttl/ttl24 $end
$var wire 1 V ttl/ttl25 $end
$var wire 1 W ttl/ttl26 $end
$var wire 1 X ttl/ttl27 $end
$var wire 1 Y ttl/ttl28 $end
$var wire 1 Z ttl/ttl29 $end
$var wire 1 [ ttl/ttl3 $end
$var wire 1 \ ttl/ttl30 $end
$var wire 1 ] ttl/ttl31 $end
$var wire 1 ^ ttl/ttl32 $end
$var wire 1 _ ttl/ttl33 $end
$var wire 1 ` ttl/ttl34 $end
$var wire 1 a ttl/ttl35 $end
$var wire 1 b ttl/ttl36 $end
$var wire 1 c ttl/ttl37 $end
$var wire 1 d ttl/ttl38 $end
$var wire 1 e ttl/ttl39 $end
$var wire 1 f ttl/ttl4 $end
$var wire 1 g ttl/ttl40 $end
$var wire 1 h ttl/ttl41 $end
$var wire 1 i ttl/ttl42 $end
$var wire 1 j ttl/ttl43 $end
$var wire 1 k ttl/ttl44 $end
$var wire 1 l ttl/ttl45 $end
$var wire 1 m ttl/ttl46 $end
$var wire 1 n ttl/ttl47 $end
$var wire 1 o ttl/ttl48 $end
$var wire 1 p ttl/ttl49 $end
$var wire 1 q ttl/ttl5 $end
$var wire 1 r ttl/ttl50 $end
$var wire 1 s ttl/ttl51 $end
$var wire 1 t ttl/ttl52 $end
$var wire 1 u ttl/ttl53 $end
$var wire 1 v ttl/ttl54 $end
$var wire 1 w ttl/ttl55 $end
$var wire 1 x ttl/ttl56 $end
$var wire 1 y ttl/ttl57 $end
$var wire 1 z ttl/ttl58 $end
$var wire 1 { ttl/ttl59 $end
$var wire 1 | ttl/ttl6 $end
$var wire 1 } ttl/ttl60 $end
$var wire 1 ~ ttl/ttl61 $end
$var wire 1 "! ttl/ttl62 $end
$var wire 1 "" ttl/ttl63 $end
$var wire 1 "# ttl/ttl7 $end
$var wire 1 "$ ttl/ttl8 $end
$var wire 1 "% ttl/ttl9 $end
$var wire 1 "& ttl/ttl_mirny0_sw0 $end
$var wire 1 "' ttl/ttl_mirny0_sw1 $end
$var wire 1 "( ttl/ttl_mirny0_sw2 $end
$var wire 1 ") ttl/ttl_mirny0_sw3 $end
$var wire 1 "* ttl/ttl_urukul0_io_update $end
$var wire 1 "+ ttl/ttl_urukul0_sw0 $end
$var wire 1 ", ttl/ttl_urukul0_sw1 $end
$var wire 1 "- ttl/ttl_urukul0_sw2 $end
$var wire 1 ". ttl/ttl_urukul0_sw3 $end
$var wire 1 "/ ttl/ttl_urukul1_io_update $end
$var wire 1 "0 ttl/ttl_zotino0_clr $end
$var wire 1 "1 ttl/ttl_zotino0_ldac $end
$var wire 1 "2 ttl/ttl_zotino1_clr $end
$var wire 1 "3 ttl/ttl_zotino1_ldac $end
$var wire 64 "4 rtio_slack $end
#0
16
06
b00000010 :
b00000010 9
b00000111 8
b00000010 7
b0011111100100000001100101000010111000001110100111111110111110111 "4
#8
16
06
b00010000000000000000000000000000 ;
b0011111100100000000110100101110100000001000101011000011101011010 "4
#304
16
06
b00000001 :
b00000010 9
b00010111 8
b00100010 7
b0011111100100000000011001111000100000111110010000010100100000010 "4
#500000312
16
06
b00000010 :
b00000010 9
b00000111 8
b00000010 7
b0011111111100000000000001111111001110001011110010101100011001011 "4
#500000320
16
06
b00000101000000000000000000000000 ;
b0011111111100000000000001111110011110011001110001100111111011110 "4
#500000616
16
06
b00000001 :
b00000010 9
b00010111 8
b00100010 7
b0011111111100000000000001111110000100000110001001011111000000010 "4
#1000000624
16
06
b00000010 :
b00000010 9
b00000111 8
b00000010 7
b0011111111110000000000000111110010100001001010100010000001111111 "4
#1000000632
16
06
b00000000000000000000000000000000 ;
b0011111111110000000000000111101111101010101000001110000111111100 "4
#1000000928
16
06
b00000001 :
b00000010 9
b00010111 8
b00100010 7
b0011111111110000000000000111101110000001011001101101100100001110 "4

      The ttl channel shows the value "x" as before.

      Without the lines addressing the leds the vcd file doesn't log any data. The file just ends after

      $var wire 64 "4 rtio_slack $end
#0

      in that case. So it's unclear to me how I "submit" the ttl events such that they show up in the log.

      Please advice how I can read out the raw analyzer buffer.