WR Artiq implementation

weidazhang

Hi @sb10q
hartytp mentioned that, you suggest to have DFF for detecting CDR phase ambiguity.
Do you mean the following?

Regards,
Weida

sb10q

It's not a problem with the CDR but with the TX path.
That circuit (or a small DDMTD core) would go on TXOUTCLK (not RXOUTCLK) and TXOUTCLK would be adjusted with the TXPI.

weidazhang

Ohh, I see. Like that?

To implement the WR we will have most of the required facility for the above anyway, i.e. the locked helper and its loop, etc,.
To instantiate another deglitch + ddmtd, and add some loop filtering and feed the stepsize should do that.
If that's what you mean.
BR,
W

sb10q

A small N is sufficient and deglitch is perhaps not needed. The helper PLL can be a MMCM.
Using the external PLL is slightly more complex (and not self-contained) but would save a MMCM.

weidazhang

sb10q
Never tried with MMCM as helper PLL, can't comment much on it.
A few thoughts still:
If the ext. helper is on the board anyway, I'd rather loop it in and save an MMCM for other usages.
If it isn't there, we can certainly reuse some of the DDMTD building blocks, and try it on a KC705.
BR,
W

sb10q

MMCM as helper works fine, we're using it on Sayma for the DAC synchronization.

hartytp

A small N is sufficient and deglitch is perhaps not needed. The helper PLL can be a MMCM.

I'm not convinced about that and it definitely needs testing. The Sayma DAC sync application seems less sensitive to jitter than the PLL, where we want to achieve a very low noise floor.

Someone needs to simulate/test this before we make that call.

hartytp

@weidazhang presumably this is something you can test somewhat easily though on the KC705.

sb10q

We are talking here about the transceiver PLL and TX divider, where the non-determinism comes in multiples of the ~ line rate UI. This has absolutely nothing to do with the CDR.
Anyway MMCM vs. external PLL is only a gateware change and uses the same hardware, so that can be easily tested.