Complex processing of the real time inputs

vli

Hi all,

A little prehistory to give a context of my couple of questions. We are planning to implement a realtime input to readout a cavity transmission, fit the Lorenzian and jump the frequency to be on resonant during the next probe. In order to do so, I am thinking of implementing RPC to use host to do the fit for the core. I have following questions that will help me understand how to improve the current solution.

I was reading the manual but I couldn't find the answer to what the host and core actually are.
I assumed from my experince with Artiq that the host is the lab computer and core is the FPGA based Kasli. Is it correct? Or is the host some CPU on the Kasli itself?

The answer then will let us understand better RPCs and what limits the speed. We have impirically observed that sampling a variable, using RPC call that returns that same variable and assigns an output of the Zotino takes at least 5ms. Is it a normal latency times?

I also was thinking about the fact that in the @kernel function run there are some arithmetical operations like 5*us or 5-2 is also possible. Is it done on the FPGA or does the host precalculates everything and then under the hood assigns the corresponding values in machine units? If FPGA is doing it, my question will be, is there a limit of functions that FPGA can do without the need for RPC?

Thanks in advance!

architeuthis

vli

I was reading the manual but I couldn't find the answer to what the host and core actually are.
I assumed from my experince with Artiq that the host is the lab computer and core is the FPGA based Kasli. Is it correct? Or is the host some CPU on the Kasli itself?

Yes, that's correct. The Kasli is the core device, and the host is any other machine that interacts with it over the network, which runs artiq_coremgmt, artiq_run, artiq_master, etc.

Is it done on the FPGA or does the host precalculates everything and then under the hood assigns the corresponding values in machine units? If FPGA is doing it, my question will be, is there a limit of functions that FPGA can do without the need for RPC?

The FPGA, or rather the MiSoC CPU implemented on the FPGA, can and does in fact do this kind of operation. Calculations are done in advance by the compiler (e.g. on the host) as much as possible to speed up the execution on the core device, and this can be expanded by assigning kernel invariants, see the corresponding section in the manual. What do you mean by limit? In general, the manual Compiler page goes into the most detail about what can and cannot be done in a kernel, but these are compiler limitations, not hardware-based.

vli

architeuthis Thanks for your reply. You are right, many things are now in the manual. I had a printed hard copy from about 4 years ago and it was missing many details. I will now read the updated manual.