Hi,
I am having trouble building a DRTIO Satellite on a KC705. When building 125 MHz variants, I got a system up and running in which a Kasli functions as master while the KC705 board I have is the satellite.
When building the 100 MHz variant of the KC705, the serial interface (while configured for 115200 Baud) seems to be running at ~ 125/100*115200 Baud. I've build my gate/firmware like this:
python kc705.py --variant NIST_QC2_Satellite --drtio100mhz
I see this problem with the variant as included in Artiq. Can you confirm that the satellite variants for KC705 work fine in your hands / for other users?
Is this a symptom if bank 12 does run at a VCCIO of 2.5V instead of 3.3V? The board I have has not been reprogrammed to run at 3.3V, but in Standalone builds I could run in different clock configurations using the Si5324 without any problems. At the end of the day I do need bank 12 to run at 2.5V for LVDS support.
When looking at the source code, my impression is that a 125 MHz reference clock is expected and that the MiSoC _RtioSysCRG for KC705 is currently setup to provide a 125 MHz sys_clk. Is there something I am missing regarding how a 100 MHz sys_clk is supposed to be generated if drtio100mhz is set? As far as I know there are 100 MHz KC705 variants out there, do you know for which versions of Artiq that is true?
Thank you for the help!
Felix