AD9910 DDS frequency error when using external clock reference

ZhangZJ

We wish to use the external clock input of the 4410 urukul DDS board in order to get a DDS signal with less phase noise. We supplied an 1GHZ external clock signal to the "EXT CLK IN" SMA port on the front panel of the urukul board, and modified the device_db.py file accordingly as follows:

device_db["urukul5_cpld"] = {
    "type": "local",
    "module": "artiq.coredevice.urukul",
    "class": "CPLD",
    "arguments": {
        "spi_device": "spi_urukul5",
        "sync_device": None,
        "io_update_device": "ttl_urukul5_io_update",
        "refclk": 1000000000.0,
        "clk_sel": 1,
        "clk_div": 1
    }
}

device_db["urukul5_ch0"] = {
    "type": "local",
    "module": "artiq.coredevice.ad9910",
    "class": "AD9910",
    "arguments": {
        "pll_n": 1,
        "pll_en": 0,
        "chip_select": 4,
        "cpld_device": "urukul5_cpld"
    }
}

device_db["urukul5_ch1"] = {
    "type": "local",
    "module": "artiq.coredevice.ad9910",
    "class": "AD9910",
    "arguments": {
        "pll_n": 1,
        "pll_en": 0,
        "chip_select": 5,
        "cpld_device": "urukul5_cpld"
    }
}

device_db["urukul5_ch2"] = {
    "type": "local",
    "module": "artiq.coredevice.ad9910",
    "class": "AD9910",
    "arguments": {
        "pll_n": 1,
        "pll_en": 0,
        "chip_select": 6,
        "cpld_device": "urukul5_cpld"
    }
}

device_db["urukul5_ch3"] = {
    "type": "local",
    "module": "artiq.coredevice.ad9910",
    "class": "AD9910",
    "arguments": {
        "pll_n": 1,
        "pll_en": 0,
        "chip_select": 7,
        "cpld_device": "urukul5_cpld"
    }
}

However, when testing the output signal with a spectrum analyzer, we surprisingly found that the frequency of the output signals of urukul5_ch1 and urukul5_ch2 is 500MHz, while I specifically use the set() function to set the DDS frequency to 200MHz. I checked that the output frequency of these two channels is fixed at 500MHz whatever frequency I set in the code, and the output power is about -0.3dBm for urukul5_ch2 and -8dBm for urukul5_ch3. Additionally, the output of urukul5_ch0 on the same DDS board is normal, and react correctly to the code. The 1GHz external clock signal has an power of 0.8dBm, which should not damage the board. I have no idea on how this issue happens, and need help on how to fix these two channels.

esavkin

Hi, do you init all the channels in the experiment? Here is the example of the code: https://git.m-labs.hk/sinara-hw/assembly/src/commit/008394c11775d9f4a1c4a78d64eeb8b8af6d2e94/src/extra/booster/dds_for_booster.py

ZhangZJ

esavkin Yes, I indeed run the full initialization code for the DDS channels. I use an init_kernel() function to conduct the same initialization process for every DDS channels, which is:

@kernel
def init_kernel(self):
    self._dds.cpld.init()
    self._dds.init()
    self._dds.set(self._freq*MHz, phase=0., amplitude=self._default_amp)
    self._dds.set_att(self._default_att)
    self._dds.cfg_sw(True)  
    self._dds.set_phase_mode(0)  
    self._dds.set_cfr1(ram_enable=0) 
    self._dds.cpld.io_update.pulse_mu(8)

Here self._dds refers to the specific DDS channel being initialized, and the attributes self._freq, self._default_amp, self._default_amp are all pre-defined. Our 4410 Urukul DDS boards has only one EEM cable, thus we use cfg_sw() function to switch it on. Essentially I think this initialization function is the same as your example.