I see that DRG mode in AD9910 data sheet describe that if I would like to enable DRG sweeping, I need to pose the pin 'DRCTL' to logic 1 either before or after I/O update pose to logic 1, now that I know how to control I/O update through specific CPLD code, yet how can I control 'DRCTL' pin?

Thank you for your help in advance.

sb10q Thank you. Not working on it yet, but it seems what I need

    21 days later

    sb10q

    Hi,
    we are trying to use the DRG to generate a linear ramp using the pull request https://github.com/m-labs/artiq/pull/2657.
    We cloned the github repo https://github.com/newell/artiq/tree/redesign-7 and entered the nix shell, but when we try to run our code we get the following error message:

    fq_red_sawtooth_DRG.py:29:9-29:28: error: this function of type method(fn=(self:<instance artiq.coredevice.ad9910.AD9910>, ?asf_profile_enable:numpy.int32, ?drg_enable:numpy.int32, ?effective_ftw:numpy.int32, ?sync_validation_disable:numpy.int32, ?matched_latency_enable:numpy.int32)->'a delay('b), self=<instance artiq.coredevice.ad9910.AD9910>) does not accept argument 'drg_nodwell_high'
    self.aom_y.set_cfr2(drg_enable=1, drg_nodwell_high=1)
    ^^^^^^^^^^^^^^^^^^^
    fq_red_sawtooth_DRG.py:29:43-29:61: note: extraneous argument
    self.aom_y.set_cfr2(drg_enable=1, drg_nodwell_high=1)

    The code is as follows:

    from artiq.experiment import *
from artiq.coredevice import ad9910

class DRG_RED_LASER(EnvExperiment):

    def build(self):
        # Set up Devices
        self.setattr_device("core")
        self.setattr_device("urukul0_ch2")
        self.aom_y = self.urukul0_ch2

        # Ramp variables
        self.ramp_low = self.aom_y.frequency_to_ftw(75.*MHz)
        self.ramp_high = self.aom_y.frequency_to_ftw(85.*MHz)
        self.ramp_step = self.aom_y.frequency_to_ftw(500*Hz)
        self.ramp_rate = 1 << 15

    @kernel
    def run(self):
        self.core.reset()

        # Initiate DDS
        self.aom_y.cpld.init()
        self.aom_y.init()
        self.aom_y.set_att(0.*dB)
        self.aom_y.set_amplitude(1.0)

        # Enable DRG
        self.aom_y.set_cfr2(drg_enable=1, drg_nodwell_high=1)

        # Set ramp limits
        self.aom_y.write64(
            ad9910._AD9910_REG_RAMP_LIMIT,
            self.ramp_high,
            self.ramp_low,
        )
     
        # Set ramp steps
        self.aom_y.write64(
            ad9910._AD9910_REG_RAMP_STEP,
            -self.ramp_step,
            self.ramp_step,
        )

        # Set ramp rate
        self.aom_y.write32(
            ad9910._AD9910_REG_RAMP_RATE,
            0xF000F000
        )

        # Send an IO update
        self.aom_y.cpld.io_update.pulse_mu(8)
        self.aom_y.sw.on()

    Trying to install the repo as a nix profile gets us the following error:

    fatal: repository 'https://github.com/newell/artiq/tree/redesign-7/' not found
    warning: could not read HEAD ref from repo at 'https://github.com/newell/artiq/tree/redesign-7', using 'master'
    fatal: repository 'https://github.com/newell/artiq/tree/redesign-7/' not found
    warning: could not update mtime for file '/home/neven/.cache/nix/gitv3/0lnzsrcdz76g4bl4hk29b6246xbq26dq5hkcr6pg6zy5zbjq53q9/refs/heads/master': error: changing modification time of '"/home/neven/.cache/nix/gitv3/0lnzsrcdz76g4bl4hk29b6246xbq26dq5hkcr6pg6zy5zbjq53q9/refs/heads/master"': No such file or directory
    evaluating derivation 'git+https://github.com/newell/artiq/tree/redesign-7#packages.x86_64-linux.default'fatal: Refusing to point HEAD outside of refs/
    warning: could not update cached head 'master' for 'https://github.com/newell/artiq/tree/redesign-7'
    error:
    … while fetching the input 'git+https://github.com/newell/artiq/tree/redesign-7'
    error: resolving Git reference 'master': revspec 'master' not found

    Note that our gateware version is 9.9038+58ea3b5.beta

    Thanks in advance.