I see that DRG mode in AD9910 data sheet describe that if I would like to enable DRG sweeping, I need to pose the pin 'DRCTL' to logic 1 either before or after I/O update pose to logic 1, now that I know how to control I/O update through specific CPLD code, yet how can I control 'DRCTL' pin?
Thank you for your help in advance.
