Depending on how tight your latency constraints are, you could simply e.g. poll the status of the input TTLs and change the output status accordingly at regular intervals, but this isn't going to be as instant as a direct hardware connection (and AFAIK can't be; the ARTIQ RTIO/kernel system makes many complex operations vastly simpler, but will always have some overhead).
If polling won't suffice, but you still want to accomplish this through ARTIQ, you may want to look into generating modified gateware with this connection built in, i.e. simply performing it directly on the FPGA as you mention. There is a beta manual page on extending ARTIQ gateware available here.