In our experiment we have the following demand for logic control of 4 TTL channels. Three of these channels should be taking input signals, marked as ttl0, ttl1 and ttl2. The fourth channel, marked as ttl_out, is set as output. We hope that the output signal of ttl_out is the same as the input of ttl1 when ttl0 is off, and the same as the input of ttl2 when ttl0 is on. To put it more clearly, we need the output of ttl_out to be (!ttl0 & ttl1) | (ttl0 & ttl2). This is a simple function for a normal FPGA developer board, but how could I accomplish this task on ARTIQ?

Depending on how tight your latency constraints are, you could simply e.g. poll the status of the input TTLs and change the output status accordingly at regular intervals, but this isn't going to be as instant as a direct hardware connection (and AFAIK can't be; the ARTIQ RTIO/kernel system makes many complex operations vastly simpler, but will always have some overhead).

If polling won't suffice, but you still want to accomplish this through ARTIQ, you may want to look into generating modified gateware with this connection built in, i.e. simply performing it directly on the FPGA as you mention. There is a beta manual page on extending ARTIQ gateware available here.