occheung
Howdy,
I messed around a bit more and potentially found a fix. I believe that despite me updating my device_db.py file, which was generated by using artiq_ddb_template -o device_db.py, I wasn't using that device_db during the flashing process. I was originally using the ./local_run.sh, but I have changed over to using artiq_coremgmt, and making sure I have the updated device_db.py in the directory of which I run the command in.
For future use:
What I changed (a lot at once, so the specific fix I'm not sure about):
I removed the hw_rev param (which should use the default value provided by the kernel) and also made sure both my urukuls had the same settings (I think in the device_db.py, urukul0 was the urukul1 in the json file, which I'm not sure why, there's a chance it wasn't but none the less). This is fine for me as I want both cards to be the same.
I set the rtio_clock on my Kasli_Soc the internal 100Mhz singal with, artiq_coremgmt -D 192.168.1.75 config write -s rtio_clock int_100
I set "refclk": 100e6, which is 100MHz,
I set the pll_en to 40 as recommended by @occheung ,
Current description.json file:
{
"target": "kasli_soc",
"min_artiq_version": "9.0",
"variant": "<varient>",
"hw_rev": "v1.1",
"base": "standalone",
"core_addr": "<IP>",
"peripherals": [
{
"type": "grabber",
"ports": [0, 1]
},
{
"type": "dio",
"board": "DIO_BNC",
"ports": [2],
"bank_direction_low": "input",
"bank_direction_high": "output"
},
{
"type": "urukul",
"dds": "ad9910",
"ports": [3],
"refclk":100e6,
"clk_sel": 0,
"pll_n": 40
},
{
"type": "sampler",
"ports": [5, 6]
},
{
"type": "fastino",
"ports": [7],
"hw_rev": "v1.1",
"log2_width": 5
},
{
"type": "urukul",
"dds": "ad9910",
"ports": [8],
"refclk":100e6,
"clk_sel": 0,
"pll_n": 40
}
]
}
After doing this I ran:
CD ~/artiq-zynq
nix develop --impure
CD src
artiq_ddb_template - o device_db.py varient.json #generate device_db.py
gateware/kasli_soc.py -g ../build/gateware varient.json #generate new gateware
make TARGET=kasli_soc GWARGS="/home/user/artiq-zynq/src/varient.json" runtime #generate new make file
exit #out of nix dev
CD src #go back into src
cp device_db.py ../build #copy device_db.py into build
CD ../build #go into build
mkbootimage boot.bif boot.bin #make new boot.bin
splits into two methods from here.
For ease of access to any potential errors connect to uart log, find out which usb port your device is plugged into:
python -m serial.tools.list_ports -v
/dev/ttyUSB2 #this was the one mine was under (I think its usually the case)
desc: Quad RS232-HS - Quad RS232-HS
stty 115200 < /dev/ttyUSB2
cat /dev/ttyUSB2
Method 1 (sd card boot):
Copy boot.bin into the SD card used for the artiq crate, then power on the crate (making sure to have switches to SD), I did this through the files system on my device, but you might need to mount the SD card then copy files onto it (ask google)
Method 2 (flash via jtag (I think its jtag)):
Inside /artiq-zynq/build:
artiq_coremgmt config write -f boot /home/user/artiq-zynq/build/boot.bin #can add -D IP if needed
artiq_coremgmt reboot
I then copied my device_db.py file into the directory in which I run my experiments, and voila, fixed.