I want to select the external clock signal .After I activate the artiq environment, I run the following code:
$ artiq_coremgmt config write -s rtio_clock e

(artiq-1) F:\artiq1>artiq_coremgmt config write -s rtio_clock e

Traceback (most recent call last):
File "C:\Users\iofs\AppData\Local\conda\conda\envs\artiq-1\Scripts\artiq_coremgmt-script.py", line 9, in <module>
sys.exit(main())
File "C:\Users\iofs\AppData\Local\conda\conda\envs\artiq-1\lib\site-packages\artiq\frontend\artiq_coremgmt.py", line 170, in main
mgmt.config_write(key, value.encode("utf-8"))
File "C:\Users\iofs\AppData\Local\conda\conda\envs\artiq-1\lib\site-packages\artiq\coredevice\comm_mgmt.py", line 168, in config_write
self._write_header(Request.ConfigWrite)
File "C:\Users\iofs\AppData\Local\conda\conda\envs\artiq-1\lib\site-packages\artiq\coredevice\comm_mgmt.py", line 81, in _write_header
self.open()
File "C:\Users\iofs\AppData\Local\conda\conda\envs\artiq-1\lib\site-packages\artiq\coredevice\comm_mgmt.py", line 65, in open
self.socket = initialize_connection(self.host, self.port, **kwargs)
File "C:\Users\iofs\AppData\Local\conda\conda\envs\artiq-1\lib\site-packages\artiq\coredevice\comm.py", line 27, in initialize_connection
sock = socket.create_connection((host, port), 5.0)
File "C:\Users\iofs\AppData\Local\conda\conda\envs\artiq-1\lib\socket.py", line 712, in create_connection
raise err
File "C:\Users\iofs\AppData\Local\conda\conda\envs\artiq-1\lib\socket.py", line 703, in create_connection
sock.connect(sa)
socket.timeout: timed out
how to solve it? After selecting an external reference successfully, is the reference signal required to be 10MHz?

Your KC705 seems not accessible from the network; check IP settings, cables, etc.

ok，I've solved it, I tried to change the reference clock to 10MHz, and it didn't work, but 125MHz was successful. Our laboratory has a 10MHz hydrogen clock reference, how can we change to 10MHz？

10MHz input is not supported on the stock KC705 firmware. You may develop it yourself, or purchase support (sales@m-labs.hk).

Or lock a nice 125MHz oscillator to your 10MHz reference and run everything off that. Wenzel sells plug-and-play modules for around $1.5k: http://www.wenzel.com/model/vhfplo/. Depending on your application, this may offer better performance - though of course it is more hardware and less convenience.

The FPGA PLL or MMCM for the IOSERDES would still be in the loop, so it is not clear if that would give better performance. It is certainly more expensive.

it is not clear if that would give better performance

Perhaps not for the IOSERDES (hence the 'Depending on your application'). I'm guessing the Wenzel module is a better clock for downstream boards like DDSs that can be clocked directly from it though? Is there a phase noise plot of a 125MHz clock generated by Kasli when clocked at 10MHz out there?

Cost is non-negligible but you only need 1 per lab.