HeavyX wishbone memory mapping

DurandA

Whilst browsing the HeavyX repository, I failed to understand how the UART peripheral is memory mapped. In the Rust firmware, UART is mapped to 0x00400000.

On the other end, the UART is connected through the Wishbone bus using (lambda a: a[20], uart.bus). Since 2²⁰ = 0x100000, how are the Wishbone peripherals mapped?

sb10q

At the moment, the mapping is a simple manual hack 🙂
Later we'll want some automation like what is done with the CSRs and the SoC builders in MiSoC (but cleaned up).
If bit 20 is set in the 32-bit (=4 bytes) Wishbone address, then it translates to (1 << 20)*4 = 0x00400000 in the CPU address space (in bytes).

DurandA

Thank you for the clarification! My goal is to add a new simple peripheral as an exercise.