I have been able to produce a working code, however when I set the address step rate to be 25 (it is defined in t_step) the DDS output cuts out. It seems that below 1e4 the step address causes problems. In the documentation on the ARTIQ website it states that the step address is defined in units of 4ns. the code is below, could someone please advise me
`from artiq.experiment import *
from artiq.coredevice import ad9910
import numpy as np
#there are 1024 values for each profile, and the control parameters are the CF, MF, and MD
#The standard value has been set as N = 1024
#first write a simple script and then looking to optimise it.
N = 1000
f1 = 99.MHz
f2 = 100.MHz
#CF, MD, and MF are all in MHz
CF = 100
MF = 0.01
MD = 1.
#Converting to time period in seconds.
time_period = (1/MF)*1000
print(time_period)
time_step= (time_period/N)
print(time_step)
t_step = int(round(time_step/4))
print(t_step)
T = int(1e8)
class DDS_freq_ramp(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("urukul1_cpld") #2nd Urukul module
self.setattr_device("urukul1_ch3") #Urukul module
self.u = self.urukul1_ch3
def prepare(self):
#create list of frequencies in FTW format to write to RAM
self.f = [0.]*N
self.f_ram = [0]*N
time = np.arange(0,1000,1)
amplitude = np.sin(2*np.pi*time/999)
amplitude2 = amplitude*MD
amplitude3 = amplitude2+CF
amplitude4 = amplitude3*MHz
f_span = f2 - f1
f_step = f_span / N
#print(f_step)
print(amplitude4)
#I want to see the first step
print(f1+f_step)
for i in range(N):
self.f[i] = amplitude4[i]
self.u.frequency_to_ram(self.f,self.f_ram)
@kernel
def run(self):
self.core.reset()
'''initialize DDS channel'''
self.u.cpld.init()
self.u.init()
self.u.cpld.io_update.pulse(100*ns)
self.core.break_realtime()
self.u.set_amplitude(1.)
self.u.set_att(0.*dB)
self.u.set(100.*MHz)
'''prepare RAM profile:'''
self.u.set_cfr1() #disable RAM for writing data
self.u.cpld.io_update.pulse_mu(8) #I/O pulse to enact RAM change
self.u.set_profile_ram(start=0, end=N-1, step=t_step, profile=0, mode=ad9910.RAM_MODE_CONT_RAMPUP)
self.u.cpld.set_profile(0)
self.u.cpld.io_update.pulse_mu(8)
'''write data to RAM:'''
delay(50*us)
self.u.write_ram(self.f_ram)
delay(100*us)
'''enable RAM mode (enacted by IO pulse) and fix other parameters:'''
self.u.set_cfr1(internal_profile=0,ram_destination=ad9910.RAM_DEST_FTW, ram_enable=1)
self.u.set_amplitude(1.)
self.u.set_att(10.*dB)
self.u.cpld.io_update.pulse_mu(8)
'''switch on DDS channel'''
self.u.sw.on() `
