Fatsie I want to include existing VHDL RTL code in a nMigen project. I can use Instance for instantiating the block inside a nMigen. I don't know how to add the VHDL file(s) so they are included when building the bitstream. Is this possible ?
sb10q Add those files to the synthesis tool using Platform.add_file in nmigen.build: https://github.com/m-labs/nmigen/blob/04c07715b41e9b0184e4e90cd1b23bfa1cb0327e/nmigen/build/plat.py#L31